Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459740 |
1 |
|
|
T20 |
137 |
|
T21 |
39 |
|
T22 |
31297 |
| auto[1] |
5278806 |
1 |
|
|
T21 |
41 |
|
T24 |
456 |
|
T28 |
1119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10544526 |
1 |
|
|
T20 |
137 |
|
T21 |
74 |
|
T22 |
31297 |
| auto[1] |
2194020 |
1 |
|
|
T21 |
6 |
|
T24 |
257 |
|
T28 |
752 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458358 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
5280188 |
1 |
|
|
T21 |
17 |
|
T24 |
511 |
|
T28 |
1455 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1561563 |
1 |
|
|
T21 |
2 |
|
T24 |
206 |
|
T28 |
422 |
| auto[1] |
auto[0] |
auto[1] |
1106893 |
1 |
|
|
T24 |
204 |
|
T28 |
423 |
|
T36 |
12 |
| auto[1] |
auto[1] |
auto[0] |
1524605 |
1 |
|
|
T21 |
9 |
|
T24 |
48 |
|
T28 |
281 |
| auto[1] |
auto[1] |
auto[1] |
1087127 |
1 |
|
|
T21 |
6 |
|
T24 |
53 |
|
T28 |
329 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |