Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426198 |
1 |
|
|
T20 |
137 |
|
T21 |
46 |
|
T22 |
31297 |
| auto[1] |
5312348 |
1 |
|
|
T21 |
34 |
|
T24 |
678 |
|
T28 |
1359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10540345 |
1 |
|
|
T20 |
137 |
|
T21 |
73 |
|
T22 |
31297 |
| auto[1] |
2198201 |
1 |
|
|
T21 |
7 |
|
T24 |
228 |
|
T28 |
790 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448258 |
1 |
|
|
T20 |
137 |
|
T21 |
58 |
|
T22 |
31297 |
| auto[1] |
5290288 |
1 |
|
|
T21 |
22 |
|
T24 |
476 |
|
T28 |
1615 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1542484 |
1 |
|
|
T21 |
3 |
|
T24 |
62 |
|
T28 |
484 |
| auto[1] |
auto[0] |
auto[1] |
1096825 |
1 |
|
|
T21 |
1 |
|
T24 |
75 |
|
T28 |
427 |
| auto[1] |
auto[1] |
auto[0] |
1549603 |
1 |
|
|
T21 |
12 |
|
T24 |
186 |
|
T28 |
341 |
| auto[1] |
auto[1] |
auto[1] |
1101376 |
1 |
|
|
T21 |
6 |
|
T24 |
153 |
|
T28 |
363 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |