Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443437 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5295109 |
1 |
|
|
T21 |
40 |
|
T24 |
667 |
|
T28 |
1490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10541278 |
1 |
|
|
T20 |
137 |
|
T21 |
70 |
|
T22 |
31297 |
| auto[1] |
2197268 |
1 |
|
|
T21 |
10 |
|
T24 |
298 |
|
T28 |
754 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431757 |
1 |
|
|
T20 |
137 |
|
T21 |
55 |
|
T22 |
31297 |
| auto[1] |
5306789 |
1 |
|
|
T21 |
25 |
|
T24 |
602 |
|
T28 |
1526 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1569626 |
1 |
|
|
T21 |
5 |
|
T24 |
166 |
|
T28 |
391 |
| auto[1] |
auto[0] |
auto[1] |
1104501 |
1 |
|
|
T21 |
4 |
|
T24 |
156 |
|
T28 |
396 |
| auto[1] |
auto[1] |
auto[0] |
1539895 |
1 |
|
|
T21 |
10 |
|
T24 |
138 |
|
T28 |
381 |
| auto[1] |
auto[1] |
auto[1] |
1092767 |
1 |
|
|
T21 |
6 |
|
T24 |
142 |
|
T28 |
358 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |