Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470601 |
1 |
|
|
T20 |
137 |
|
T21 |
47 |
|
T22 |
31297 |
| auto[1] |
5267945 |
1 |
|
|
T21 |
33 |
|
T24 |
367 |
|
T28 |
1398 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10543974 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
2194572 |
1 |
|
|
T24 |
202 |
|
T28 |
617 |
|
T36 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450883 |
1 |
|
|
T20 |
137 |
|
T21 |
77 |
|
T22 |
31297 |
| auto[1] |
5287663 |
1 |
|
|
T21 |
3 |
|
T24 |
385 |
|
T28 |
1257 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1548458 |
1 |
|
|
T21 |
3 |
|
T24 |
100 |
|
T28 |
365 |
| auto[1] |
auto[0] |
auto[1] |
1095934 |
1 |
|
|
T24 |
115 |
|
T28 |
341 |
|
T36 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1544633 |
1 |
|
|
T24 |
83 |
|
T28 |
275 |
|
T36 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1098638 |
1 |
|
|
T24 |
87 |
|
T28 |
276 |
|
T36 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |