Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424419 |
1 |
|
|
T20 |
137 |
|
T21 |
57 |
|
T22 |
31297 |
| auto[1] |
5314127 |
1 |
|
|
T21 |
23 |
|
T24 |
599 |
|
T28 |
1099 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10550100 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
2188446 |
1 |
|
|
T21 |
17 |
|
T24 |
236 |
|
T28 |
645 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450186 |
1 |
|
|
T20 |
137 |
|
T21 |
54 |
|
T22 |
31297 |
| auto[1] |
5288360 |
1 |
|
|
T21 |
26 |
|
T24 |
480 |
|
T28 |
1288 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1535657 |
1 |
|
|
T21 |
3 |
|
T24 |
85 |
|
T28 |
363 |
| auto[1] |
auto[0] |
auto[1] |
1089204 |
1 |
|
|
T21 |
12 |
|
T24 |
98 |
|
T28 |
391 |
| auto[1] |
auto[1] |
auto[0] |
1564257 |
1 |
|
|
T21 |
6 |
|
T24 |
159 |
|
T28 |
280 |
| auto[1] |
auto[1] |
auto[1] |
1099242 |
1 |
|
|
T21 |
5 |
|
T24 |
138 |
|
T28 |
254 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |