Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425529 |
1 |
|
|
T20 |
137 |
|
T21 |
64 |
|
T22 |
31297 |
| auto[1] |
5313017 |
1 |
|
|
T21 |
16 |
|
T24 |
673 |
|
T28 |
1612 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10542479 |
1 |
|
|
T20 |
137 |
|
T21 |
73 |
|
T22 |
31297 |
| auto[1] |
2196067 |
1 |
|
|
T21 |
7 |
|
T24 |
240 |
|
T28 |
721 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7429308 |
1 |
|
|
T20 |
137 |
|
T21 |
69 |
|
T22 |
31297 |
| auto[1] |
5309238 |
1 |
|
|
T21 |
11 |
|
T24 |
492 |
|
T28 |
1397 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1562432 |
1 |
|
|
T21 |
2 |
|
T24 |
141 |
|
T28 |
279 |
| auto[1] |
auto[0] |
auto[1] |
1097517 |
1 |
|
|
T21 |
7 |
|
T24 |
131 |
|
T28 |
292 |
| auto[1] |
auto[1] |
auto[0] |
1550739 |
1 |
|
|
T21 |
2 |
|
T24 |
111 |
|
T28 |
397 |
| auto[1] |
auto[1] |
auto[1] |
1098550 |
1 |
|
|
T24 |
109 |
|
T28 |
429 |
|
T36 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |