Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449606 |
1 |
|
|
T20 |
137 |
|
T21 |
51 |
|
T22 |
31297 |
| auto[1] |
5288940 |
1 |
|
|
T21 |
29 |
|
T24 |
597 |
|
T28 |
1887 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10536982 |
1 |
|
|
T20 |
137 |
|
T21 |
69 |
|
T22 |
31297 |
| auto[1] |
2201564 |
1 |
|
|
T21 |
11 |
|
T24 |
287 |
|
T28 |
586 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435524 |
1 |
|
|
T20 |
137 |
|
T21 |
67 |
|
T22 |
31297 |
| auto[1] |
5303022 |
1 |
|
|
T21 |
13 |
|
T24 |
562 |
|
T28 |
1116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1549288 |
1 |
|
|
T24 |
121 |
|
T28 |
185 |
|
T36 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1105040 |
1 |
|
|
T21 |
3 |
|
T24 |
120 |
|
T28 |
202 |
| auto[1] |
auto[1] |
auto[0] |
1552170 |
1 |
|
|
T21 |
2 |
|
T24 |
154 |
|
T28 |
345 |
| auto[1] |
auto[1] |
auto[1] |
1096524 |
1 |
|
|
T21 |
8 |
|
T24 |
167 |
|
T28 |
384 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |