Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7414061 |
1 |
|
|
T20 |
137 |
|
T21 |
46 |
|
T22 |
31297 |
| auto[1] |
5324485 |
1 |
|
|
T21 |
34 |
|
T24 |
438 |
|
T28 |
1629 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10550281 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
2188265 |
1 |
|
|
T24 |
319 |
|
T28 |
870 |
|
T36 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462043 |
1 |
|
|
T20 |
137 |
|
T21 |
75 |
|
T22 |
31297 |
| auto[1] |
5276503 |
1 |
|
|
T21 |
5 |
|
T24 |
633 |
|
T28 |
1799 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1537880 |
1 |
|
|
T24 |
205 |
|
T28 |
475 |
|
T36 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1093949 |
1 |
|
|
T24 |
227 |
|
T28 |
427 |
|
T36 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1550358 |
1 |
|
|
T21 |
5 |
|
T24 |
109 |
|
T28 |
454 |
| auto[1] |
auto[1] |
auto[1] |
1094316 |
1 |
|
|
T24 |
92 |
|
T28 |
443 |
|
T36 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |