Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7420398 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5318148 |
1 |
|
|
T21 |
40 |
|
T24 |
727 |
|
T28 |
1530 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10535355 |
1 |
|
|
T20 |
137 |
|
T21 |
72 |
|
T22 |
31297 |
| auto[1] |
2203191 |
1 |
|
|
T21 |
8 |
|
T24 |
192 |
|
T28 |
669 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435614 |
1 |
|
|
T20 |
137 |
|
T21 |
58 |
|
T22 |
31297 |
| auto[1] |
5302932 |
1 |
|
|
T21 |
22 |
|
T24 |
424 |
|
T28 |
1286 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1548557 |
1 |
|
|
T24 |
79 |
|
T28 |
337 |
|
T36 |
17 |
| auto[1] |
auto[0] |
auto[1] |
1098239 |
1 |
|
|
T21 |
5 |
|
T24 |
95 |
|
T28 |
393 |
| auto[1] |
auto[1] |
auto[0] |
1551184 |
1 |
|
|
T21 |
14 |
|
T24 |
153 |
|
T28 |
280 |
| auto[1] |
auto[1] |
auto[1] |
1104952 |
1 |
|
|
T21 |
3 |
|
T24 |
97 |
|
T28 |
276 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |