Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443062 |
1 |
|
|
T20 |
137 |
|
T21 |
44 |
|
T22 |
31297 |
| auto[1] |
5295484 |
1 |
|
|
T21 |
36 |
|
T24 |
604 |
|
T28 |
1825 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10537138 |
1 |
|
|
T20 |
137 |
|
T21 |
69 |
|
T22 |
31297 |
| auto[1] |
2201408 |
1 |
|
|
T21 |
11 |
|
T24 |
261 |
|
T28 |
606 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435438 |
1 |
|
|
T20 |
137 |
|
T21 |
56 |
|
T22 |
31297 |
| auto[1] |
5303108 |
1 |
|
|
T21 |
24 |
|
T24 |
477 |
|
T28 |
1269 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1554991 |
1 |
|
|
T21 |
4 |
|
T24 |
96 |
|
T28 |
244 |
| auto[1] |
auto[0] |
auto[1] |
1101479 |
1 |
|
|
T21 |
3 |
|
T24 |
135 |
|
T28 |
255 |
| auto[1] |
auto[1] |
auto[0] |
1546709 |
1 |
|
|
T21 |
9 |
|
T24 |
120 |
|
T28 |
419 |
| auto[1] |
auto[1] |
auto[1] |
1099929 |
1 |
|
|
T21 |
8 |
|
T24 |
126 |
|
T28 |
351 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |