Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434360 |
1 |
|
|
T20 |
137 |
|
T21 |
57 |
|
T22 |
31297 |
| auto[1] |
5304186 |
1 |
|
|
T21 |
23 |
|
T24 |
516 |
|
T28 |
1535 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12059069 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
679477 |
1 |
|
|
T21 |
1 |
|
T24 |
117 |
|
T28 |
275 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425741 |
1 |
|
|
T20 |
137 |
|
T21 |
49 |
|
T22 |
31297 |
| auto[1] |
5312805 |
1 |
|
|
T21 |
31 |
|
T24 |
562 |
|
T28 |
1382 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2324259 |
1 |
|
|
T21 |
26 |
|
T24 |
194 |
|
T28 |
429 |
| auto[1] |
auto[0] |
auto[1] |
340555 |
1 |
|
|
T21 |
1 |
|
T24 |
55 |
|
T28 |
109 |
| auto[1] |
auto[1] |
auto[0] |
2309069 |
1 |
|
|
T21 |
4 |
|
T24 |
251 |
|
T28 |
678 |
| auto[1] |
auto[1] |
auto[1] |
338922 |
1 |
|
|
T24 |
62 |
|
T28 |
166 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |