Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469461 |
1 |
|
|
T20 |
137 |
|
T21 |
59 |
|
T22 |
31297 |
| auto[1] |
5269085 |
1 |
|
|
T21 |
21 |
|
T24 |
431 |
|
T28 |
1439 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10544908 |
1 |
|
|
T20 |
137 |
|
T21 |
62 |
|
T22 |
31297 |
| auto[1] |
2193638 |
1 |
|
|
T21 |
18 |
|
T24 |
225 |
|
T28 |
632 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443924 |
1 |
|
|
T20 |
137 |
|
T21 |
57 |
|
T22 |
31297 |
| auto[1] |
5294622 |
1 |
|
|
T21 |
23 |
|
T24 |
442 |
|
T28 |
1326 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1564489 |
1 |
|
|
T21 |
3 |
|
T24 |
139 |
|
T28 |
367 |
| auto[1] |
auto[0] |
auto[1] |
1105985 |
1 |
|
|
T21 |
18 |
|
T24 |
152 |
|
T28 |
348 |
| auto[1] |
auto[1] |
auto[0] |
1536495 |
1 |
|
|
T21 |
2 |
|
T24 |
78 |
|
T28 |
327 |
| auto[1] |
auto[1] |
auto[1] |
1087653 |
1 |
|
|
T24 |
73 |
|
T28 |
284 |
|
T36 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |