Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460240 |
1 |
|
|
T20 |
137 |
|
T21 |
58 |
|
T22 |
31297 |
| auto[1] |
5278306 |
1 |
|
|
T21 |
22 |
|
T24 |
586 |
|
T28 |
1644 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10542669 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
2195877 |
1 |
|
|
T24 |
198 |
|
T28 |
717 |
|
T36 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458213 |
1 |
|
|
T20 |
137 |
|
T21 |
71 |
|
T22 |
31297 |
| auto[1] |
5280333 |
1 |
|
|
T21 |
9 |
|
T24 |
421 |
|
T28 |
1503 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1539706 |
1 |
|
|
T21 |
9 |
|
T24 |
84 |
|
T28 |
397 |
| auto[1] |
auto[0] |
auto[1] |
1097705 |
1 |
|
|
T24 |
95 |
|
T28 |
375 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1544750 |
1 |
|
|
T24 |
139 |
|
T28 |
389 |
|
T36 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1098172 |
1 |
|
|
T24 |
103 |
|
T28 |
342 |
|
T1 |
16850 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |