Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447707 |
1 |
|
|
T20 |
137 |
|
T21 |
68 |
|
T22 |
31297 |
| auto[1] |
5290839 |
1 |
|
|
T21 |
12 |
|
T24 |
330 |
|
T28 |
1383 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10544210 |
1 |
|
|
T20 |
137 |
|
T21 |
71 |
|
T22 |
31297 |
| auto[1] |
2194336 |
1 |
|
|
T21 |
9 |
|
T24 |
252 |
|
T28 |
751 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7457894 |
1 |
|
|
T20 |
137 |
|
T21 |
65 |
|
T22 |
31297 |
| auto[1] |
5280652 |
1 |
|
|
T21 |
15 |
|
T24 |
538 |
|
T28 |
1518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1562219 |
1 |
|
|
T21 |
1 |
|
T24 |
204 |
|
T28 |
355 |
| auto[1] |
auto[0] |
auto[1] |
1105405 |
1 |
|
|
T21 |
8 |
|
T24 |
182 |
|
T28 |
390 |
| auto[1] |
auto[1] |
auto[0] |
1524097 |
1 |
|
|
T21 |
5 |
|
T24 |
82 |
|
T28 |
412 |
| auto[1] |
auto[1] |
auto[1] |
1088931 |
1 |
|
|
T21 |
1 |
|
T24 |
70 |
|
T28 |
361 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |