Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449314 |
1 |
|
|
T20 |
137 |
|
T21 |
58 |
|
T22 |
31297 |
| auto[1] |
5289232 |
1 |
|
|
T21 |
22 |
|
T24 |
581 |
|
T28 |
1137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12058342 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
680204 |
1 |
|
|
T21 |
1 |
|
T24 |
106 |
|
T28 |
295 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426121 |
1 |
|
|
T20 |
137 |
|
T21 |
53 |
|
T22 |
31297 |
| auto[1] |
5312425 |
1 |
|
|
T21 |
27 |
|
T24 |
558 |
|
T28 |
1453 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2322368 |
1 |
|
|
T21 |
19 |
|
T24 |
165 |
|
T28 |
671 |
| auto[1] |
auto[0] |
auto[1] |
341145 |
1 |
|
|
T24 |
40 |
|
T28 |
177 |
|
T36 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2309853 |
1 |
|
|
T21 |
7 |
|
T24 |
287 |
|
T28 |
487 |
| auto[1] |
auto[1] |
auto[1] |
339059 |
1 |
|
|
T21 |
1 |
|
T24 |
66 |
|
T28 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |