Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459201 |
1 |
|
|
T20 |
137 |
|
T21 |
69 |
|
T22 |
31297 |
| auto[1] |
5279345 |
1 |
|
|
T21 |
11 |
|
T24 |
355 |
|
T28 |
1231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12057577 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
680969 |
1 |
|
|
T21 |
1 |
|
T24 |
120 |
|
T28 |
246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7420977 |
1 |
|
|
T20 |
137 |
|
T21 |
54 |
|
T22 |
31297 |
| auto[1] |
5317569 |
1 |
|
|
T21 |
26 |
|
T24 |
642 |
|
T28 |
1245 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2324535 |
1 |
|
|
T21 |
21 |
|
T24 |
368 |
|
T28 |
615 |
| auto[1] |
auto[0] |
auto[1] |
341511 |
1 |
|
|
T21 |
1 |
|
T24 |
82 |
|
T28 |
156 |
| auto[1] |
auto[1] |
auto[0] |
2312065 |
1 |
|
|
T21 |
4 |
|
T24 |
154 |
|
T28 |
384 |
| auto[1] |
auto[1] |
auto[1] |
339458 |
1 |
|
|
T24 |
38 |
|
T28 |
90 |
|
T36 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |