Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460351 |
1 |
|
|
T20 |
137 |
|
T21 |
47 |
|
T22 |
31297 |
| auto[1] |
5278195 |
1 |
|
|
T21 |
33 |
|
T24 |
629 |
|
T28 |
1597 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12060317 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
678229 |
1 |
|
|
T24 |
124 |
|
T28 |
323 |
|
T36 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439674 |
1 |
|
|
T20 |
137 |
|
T21 |
68 |
|
T22 |
31297 |
| auto[1] |
5298872 |
1 |
|
|
T21 |
12 |
|
T24 |
655 |
|
T28 |
1599 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2319599 |
1 |
|
|
T24 |
209 |
|
T28 |
534 |
|
T36 |
21 |
| auto[1] |
auto[0] |
auto[1] |
340235 |
1 |
|
|
T24 |
46 |
|
T28 |
136 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2301044 |
1 |
|
|
T21 |
12 |
|
T24 |
322 |
|
T28 |
742 |
| auto[1] |
auto[1] |
auto[1] |
337994 |
1 |
|
|
T24 |
78 |
|
T28 |
187 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |