Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440830 |
1 |
|
|
T20 |
137 |
|
T21 |
56 |
|
T22 |
31297 |
| auto[1] |
5297716 |
1 |
|
|
T21 |
24 |
|
T24 |
422 |
|
T28 |
1681 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12062702 |
1 |
|
|
T20 |
137 |
|
T21 |
80 |
|
T22 |
31297 |
| auto[1] |
675844 |
1 |
|
|
T24 |
118 |
|
T28 |
309 |
|
T36 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450031 |
1 |
|
|
T20 |
137 |
|
T21 |
58 |
|
T22 |
31297 |
| auto[1] |
5288515 |
1 |
|
|
T21 |
22 |
|
T24 |
608 |
|
T28 |
1677 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2304160 |
1 |
|
|
T21 |
19 |
|
T24 |
272 |
|
T28 |
583 |
| auto[1] |
auto[0] |
auto[1] |
337538 |
1 |
|
|
T24 |
60 |
|
T28 |
127 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2308511 |
1 |
|
|
T21 |
3 |
|
T24 |
218 |
|
T28 |
785 |
| auto[1] |
auto[1] |
auto[1] |
338306 |
1 |
|
|
T24 |
58 |
|
T28 |
182 |
|
T36 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |