Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453257 |
1 |
|
|
T20 |
137 |
|
T21 |
47 |
|
T22 |
31297 |
| auto[1] |
5285289 |
1 |
|
|
T21 |
33 |
|
T24 |
458 |
|
T28 |
1562 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12063813 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
674733 |
1 |
|
|
T21 |
1 |
|
T24 |
60 |
|
T28 |
252 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459839 |
1 |
|
|
T20 |
137 |
|
T21 |
40 |
|
T22 |
31297 |
| auto[1] |
5278707 |
1 |
|
|
T21 |
40 |
|
T24 |
358 |
|
T28 |
1244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2313973 |
1 |
|
|
T21 |
22 |
|
T24 |
181 |
|
T28 |
394 |
| auto[1] |
auto[0] |
auto[1] |
339897 |
1 |
|
|
T24 |
37 |
|
T28 |
101 |
|
T1 |
3609 |
| auto[1] |
auto[1] |
auto[0] |
2290001 |
1 |
|
|
T21 |
17 |
|
T24 |
117 |
|
T28 |
598 |
| auto[1] |
auto[1] |
auto[1] |
334836 |
1 |
|
|
T21 |
1 |
|
T24 |
23 |
|
T28 |
151 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |