Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442930 |
1 |
|
|
T20 |
137 |
|
T21 |
57 |
|
T22 |
31297 |
| auto[1] |
5295616 |
1 |
|
|
T21 |
23 |
|
T24 |
608 |
|
T28 |
1159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12066928 |
1 |
|
|
T20 |
137 |
|
T21 |
79 |
|
T22 |
31297 |
| auto[1] |
671618 |
1 |
|
|
T21 |
1 |
|
T24 |
104 |
|
T28 |
238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474191 |
1 |
|
|
T20 |
137 |
|
T21 |
63 |
|
T22 |
31297 |
| auto[1] |
5264355 |
1 |
|
|
T21 |
17 |
|
T24 |
511 |
|
T28 |
1256 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2316552 |
1 |
|
|
T21 |
7 |
|
T24 |
173 |
|
T28 |
624 |
| auto[1] |
auto[0] |
auto[1] |
340126 |
1 |
|
|
T24 |
46 |
|
T28 |
148 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2276185 |
1 |
|
|
T21 |
9 |
|
T24 |
234 |
|
T28 |
394 |
| auto[1] |
auto[1] |
auto[1] |
331492 |
1 |
|
|
T21 |
1 |
|
T24 |
58 |
|
T28 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |