Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3510653	1			T23	1		T24	1		T25	707
all_pins[1]	3510653	1			T23	1		T24	1		T25	707
all_pins[2]	3510653	1			T23	1		T24	1		T25	707
all_pins[3]	3510653	1			T23	1		T24	1		T25	707
all_pins[4]	3510653	1			T23	1		T24	1		T25	707
all_pins[5]	3510653	1			T23	1		T24	1		T25	707
all_pins[6]	3510653	1			T23	1		T24	1		T25	707
all_pins[7]	3510653	1			T23	1		T24	1		T25	707
all_pins[8]	3510653	1			T23	1		T24	1		T25	707
all_pins[9]	3510653	1			T23	1		T24	1		T25	707
all_pins[10]	3510653	1			T23	1		T24	1		T25	707
all_pins[11]	3510653	1			T23	1		T24	1		T25	707
all_pins[12]	3510653	1			T23	1		T24	1		T25	707
all_pins[13]	3510653	1			T23	1		T24	1		T25	707
all_pins[14]	3510653	1			T23	1		T24	1		T25	707
all_pins[15]	3510653	1			T23	1		T24	1		T25	707
all_pins[16]	3510653	1			T23	1		T24	1		T25	707
all_pins[17]	3510653	1			T23	1		T24	1		T25	707
all_pins[18]	3510653	1			T23	1		T24	1		T25	707
all_pins[19]	3510653	1			T23	1		T24	1		T25	707
all_pins[20]	3510653	1			T23	1		T24	1		T25	707
all_pins[21]	3510653	1			T23	1		T24	1		T25	707
all_pins[22]	3510653	1			T23	1		T24	1		T25	707
all_pins[23]	3510653	1			T23	1		T24	1		T25	707
all_pins[24]	3510653	1			T23	1		T24	1		T25	707
all_pins[25]	3510653	1			T23	1		T24	1		T25	707
all_pins[26]	3510653	1			T23	1		T24	1		T25	707
all_pins[27]	3510653	1			T23	1		T24	1		T25	707
all_pins[28]	3510653	1			T23	1		T24	1		T25	707
all_pins[29]	3510653	1			T23	1		T24	1		T25	707
all_pins[30]	3510653	1			T23	1		T24	1		T25	707
all_pins[31]	3510653	1			T23	1		T24	1		T25	707

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	69806293	1			T23	32		T24	32		T25	14151
values[0x1]	42534603	1			T25	8473		T28	3890		T29	55
transitions[0x0=>0x1]	25482440	1			T25	5100		T28	2273		T29	44
transitions[0x1=>0x0]	25482274	1			T25	5099		T28	2273		T29	44

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2178782	1			T23	1		T24	1		T25	460
all_pins[0]	values[0x1]	1331871	1			T25	247		T28	137		T29	2
all_pins[0]	transitions[0x0=>0x1]	822899	1			T25	165		T28	101		T29	2
all_pins[0]	transitions[0x1=>0x0]	824145	1			T25	198		T28	71		T30	4
all_pins[1]	values[0x0]	2184345	1			T23	1		T24	1		T25	440
all_pins[1]	values[0x1]	1326308	1			T25	267		T28	94		T29	4
all_pins[1]	transitions[0x0=>0x1]	792032	1			T25	182		T28	52		T29	4
all_pins[1]	transitions[0x1=>0x0]	797595	1			T25	162		T28	95		T29	2
all_pins[2]	values[0x0]	2186408	1			T23	1		T24	1		T25	512
all_pins[2]	values[0x1]	1324245	1			T25	195		T28	111		T29	1
all_pins[2]	transitions[0x0=>0x1]	793181	1			T25	137		T28	74		T30	1
all_pins[2]	transitions[0x1=>0x0]	795244	1			T25	209		T28	57		T29	3
all_pins[3]	values[0x0]	2182903	1			T23	1		T24	1		T25	463
all_pins[3]	values[0x1]	1327750	1			T25	244		T28	114		T29	2
all_pins[3]	transitions[0x0=>0x1]	795772	1			T25	144		T28	53		T29	1
all_pins[3]	transitions[0x1=>0x0]	792267	1			T25	95		T28	50		T30	2
all_pins[4]	values[0x0]	2180175	1			T23	1		T24	1		T25	379
all_pins[4]	values[0x1]	1330478	1			T25	328		T28	112		T30	10
all_pins[4]	transitions[0x0=>0x1]	796307	1			T25	218		T28	67		T30	6
all_pins[4]	transitions[0x1=>0x0]	793579	1			T25	134		T28	69		T29	2
all_pins[5]	values[0x0]	2188158	1			T23	1		T24	1		T25	383
all_pins[5]	values[0x1]	1322495	1			T25	324		T28	108		T29	7
all_pins[5]	transitions[0x0=>0x1]	789607	1			T25	167		T28	66		T29	7
all_pins[5]	transitions[0x1=>0x0]	797590	1			T25	171		T28	70		T30	8
all_pins[6]	values[0x0]	2176442	1			T23	1		T24	1		T25	498
all_pins[6]	values[0x1]	1334211	1			T25	209		T28	143		T29	3
all_pins[6]	transitions[0x0=>0x1]	801812	1			T25	86		T28	95		T30	6
all_pins[6]	transitions[0x1=>0x0]	790096	1			T25	201		T28	60		T29	4
all_pins[7]	values[0x0]	2183650	1			T23	1		T24	1		T25	455
all_pins[7]	values[0x1]	1327003	1			T25	252		T28	113		T30	12
all_pins[7]	transitions[0x0=>0x1]	790929	1			T25	184		T28	65		T30	5
all_pins[7]	transitions[0x1=>0x0]	798137	1			T25	141		T28	95		T29	3
all_pins[8]	values[0x0]	2180434	1			T23	1		T24	1		T25	416
all_pins[8]	values[0x1]	1330219	1			T25	291		T28	150		T29	4
all_pins[8]	transitions[0x0=>0x1]	796951	1			T25	181		T28	107		T29	4
all_pins[8]	transitions[0x1=>0x0]	793735	1			T25	142		T28	70		T30	8
all_pins[9]	values[0x0]	2180584	1			T23	1		T24	1		T25	412
all_pins[9]	values[0x1]	1330069	1			T25	295		T28	147		T30	7
all_pins[9]	transitions[0x0=>0x1]	795380	1			T25	162		T28	75		T30	3
all_pins[9]	transitions[0x1=>0x0]	795530	1			T25	158		T28	78		T29	4
all_pins[10]	values[0x0]	2182736	1			T23	1		T24	1		T25	411
all_pins[10]	values[0x1]	1327917	1			T25	296		T28	120		T30	9
all_pins[10]	transitions[0x0=>0x1]	798222	1			T25	184		T28	50		T30	7
all_pins[10]	transitions[0x1=>0x0]	800374	1			T25	183		T28	77		T30	5
all_pins[11]	values[0x0]	2178500	1			T23	1		T24	1		T25	422
all_pins[11]	values[0x1]	1332153	1			T25	285		T28	158		T30	9
all_pins[11]	transitions[0x0=>0x1]	796383	1			T25	175		T28	86		T30	5
all_pins[11]	transitions[0x1=>0x0]	792147	1			T25	186		T28	48		T30	5
all_pins[12]	values[0x0]	2181912	1			T23	1		T24	1		T25	431
all_pins[12]	values[0x1]	1328741	1			T25	276		T28	74		T29	1
all_pins[12]	transitions[0x0=>0x1]	793738	1			T25	152		T28	54		T29	1
all_pins[12]	transitions[0x1=>0x0]	797150	1			T25	161		T28	138		T30	5
all_pins[13]	values[0x0]	2183383	1			T23	1		T24	1		T25	426
all_pins[13]	values[0x1]	1327270	1			T25	281		T28	101		T29	2
all_pins[13]	transitions[0x0=>0x1]	795087	1			T25	173		T28	74		T29	2
all_pins[13]	transitions[0x1=>0x0]	796558	1			T25	168		T28	47		T29	1
all_pins[14]	values[0x0]	2175401	1			T23	1		T24	1		T25	470
all_pins[14]	values[0x1]	1335252	1			T25	237		T28	98		T30	8
all_pins[14]	transitions[0x0=>0x1]	798881	1			T25	157		T28	57		T30	4
all_pins[14]	transitions[0x1=>0x0]	790899	1			T25	201		T28	60		T29	2
all_pins[15]	values[0x0]	2178167	1			T23	1		T24	1		T25	392
all_pins[15]	values[0x1]	1332486	1			T25	315		T28	158		T29	2
all_pins[15]	transitions[0x0=>0x1]	797618	1			T25	207		T28	113		T29	2
all_pins[15]	transitions[0x1=>0x0]	800384	1			T25	129		T28	53		T30	6
all_pins[16]	values[0x0]	2183723	1			T23	1		T24	1		T25	454
all_pins[16]	values[0x1]	1326930	1			T25	253		T28	138		T29	1
all_pins[16]	transitions[0x0=>0x1]	794218	1			T25	126		T28	72		T29	1
all_pins[16]	transitions[0x1=>0x0]	799774	1			T25	188		T28	92		T29	2
all_pins[17]	values[0x0]	2185638	1			T23	1		T24	1		T25	478
all_pins[17]	values[0x1]	1325015	1			T25	229		T28	139		T29	4
all_pins[17]	transitions[0x0=>0x1]	794489	1			T25	126		T28	72		T29	4
all_pins[17]	transitions[0x1=>0x0]	796404	1			T25	150		T28	71		T29	1
all_pins[18]	values[0x0]	2182462	1			T23	1		T24	1		T25	493
all_pins[18]	values[0x1]	1328191	1			T25	214		T28	153		T29	4
all_pins[18]	transitions[0x0=>0x1]	798233	1			T25	136		T28	102		T29	1
all_pins[18]	transitions[0x1=>0x0]	795057	1			T25	151		T28	88		T29	1
all_pins[19]	values[0x0]	2177027	1			T23	1		T24	1		T25	471
all_pins[19]	values[0x1]	1333626	1			T25	236		T28	80		T30	6
all_pins[19]	transitions[0x0=>0x1]	799368	1			T25	160		T28	48		T30	2
all_pins[19]	transitions[0x1=>0x0]	793933	1			T25	138		T28	121		T29	4
all_pins[20]	values[0x0]	2183055	1			T23	1		T24	1		T25	420
all_pins[20]	values[0x1]	1327598	1			T25	287		T28	119		T30	13
all_pins[20]	transitions[0x0=>0x1]	791737	1			T25	183		T28	86		T30	10
all_pins[20]	transitions[0x1=>0x0]	797765	1			T25	132		T28	47		T30	3
all_pins[21]	values[0x0]	2181818	1			T23	1		T24	1		T25	432
all_pins[21]	values[0x1]	1328835	1			T25	275		T28	108		T29	4
all_pins[21]	transitions[0x0=>0x1]	795814	1			T25	144		T28	63		T29	4
all_pins[21]	transitions[0x1=>0x0]	794577	1			T25	156		T28	74		T30	12
all_pins[22]	values[0x0]	2180714	1			T23	1		T24	1		T25	462
all_pins[22]	values[0x1]	1329939	1			T25	245		T28	154		T29	1
all_pins[22]	transitions[0x0=>0x1]	796038	1			T25	147		T28	72		T30	2
all_pins[22]	transitions[0x1=>0x0]	794934	1			T25	177		T28	26		T29	3
all_pins[23]	values[0x0]	2184803	1			T23	1		T24	1		T25	498
all_pins[23]	values[0x1]	1325850	1			T25	209		T28	112		T29	3
all_pins[23]	transitions[0x0=>0x1]	794008	1			T25	111		T28	44		T29	2
all_pins[23]	transitions[0x1=>0x0]	798097	1			T25	147		T28	86		T32	187
all_pins[24]	values[0x0]	2181361	1			T23	1		T24	1		T25	494
all_pins[24]	values[0x1]	1329292	1			T25	213		T28	138		T29	1
all_pins[24]	transitions[0x0=>0x1]	796339	1			T25	159		T28	95		T30	1
all_pins[24]	transitions[0x1=>0x0]	792897	1			T25	155		T28	69		T29	2
all_pins[25]	values[0x0]	2182009	1			T23	1		T24	1		T25	330
all_pins[25]	values[0x1]	1328644	1			T25	377		T28	124		T30	5
all_pins[25]	transitions[0x0=>0x1]	794210	1			T25	238		T28	75		T30	4
all_pins[25]	transitions[0x1=>0x0]	794858	1			T25	74		T28	89		T29	1
all_pins[26]	values[0x0]	2179107	1			T23	1		T24	1		T25	449
all_pins[26]	values[0x1]	1331546	1			T25	258		T28	156		T29	2
all_pins[26]	transitions[0x0=>0x1]	795532	1			T25	114		T28	72		T29	2
all_pins[26]	transitions[0x1=>0x0]	792630	1			T25	233		T28	40		T30	4
all_pins[27]	values[0x0]	2175395	1			T23	1		T24	1		T25	465
all_pins[27]	values[0x1]	1335258	1			T25	242		T28	114		T30	7
all_pins[27]	transitions[0x0=>0x1]	799248	1			T25	145		T28	49		T30	6
all_pins[27]	transitions[0x1=>0x0]	795536	1			T25	161		T28	91		T29	2
all_pins[28]	values[0x0]	2181904	1			T23	1		T24	1		T25	417
all_pins[28]	values[0x1]	1328749	1			T25	290		T28	102		T29	1
all_pins[28]	transitions[0x0=>0x1]	790954	1			T25	183		T28	39		T29	1
all_pins[28]	transitions[0x1=>0x0]	797463	1			T25	135		T28	51		T30	3
all_pins[29]	values[0x0]	2181690	1			T23	1		T24	1		T25	455
all_pins[29]	values[0x1]	1328963	1			T25	252		T28	131		T30	6
all_pins[29]	transitions[0x0=>0x1]	796300	1			T25	137		T28	81		T30	2
all_pins[29]	transitions[0x1=>0x0]	796086	1			T25	175		T28	52		T29	1
all_pins[30]	values[0x0]	2186237	1			T23	1		T24	1		T25	437
all_pins[30]	values[0x1]	1324416	1			T25	270		T28	77		T29	6
all_pins[30]	transitions[0x0=>0x1]	791466	1			T25	165		T28	39		T29	6
all_pins[30]	transitions[0x1=>0x0]	796013	1			T25	147		T28	93		T30	2
all_pins[31]	values[0x0]	2177370	1			T23	1		T24	1		T25	426
all_pins[31]	values[0x1]	1333283	1			T25	281		T28	107		T30	10
all_pins[31]	transitions[0x0=>0x1]	799687	1			T25	152		T28	75		T30	2
all_pins[31]	transitions[0x1=>0x0]	790820	1			T25	141		T28	45		T29	6