Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12220841	1			T23	95		T24	175		T25	1852
all_values[1]	12220841	1			T23	95		T24	175		T25	1852
all_values[2]	12220841	1			T23	95		T24	175		T25	1852
all_values[3]	12220841	1			T23	95		T24	175		T25	1852
all_values[4]	12220841	1			T23	95		T24	175		T25	1852
all_values[5]	12220841	1			T23	95		T24	175		T25	1852
all_values[6]	12220841	1			T23	95		T24	175		T25	1852
all_values[7]	12220841	1			T23	95		T24	175		T25	1852
all_values[8]	12220841	1			T23	95		T24	175		T25	1852
all_values[9]	12220841	1			T23	95		T24	175		T25	1852
all_values[10]	12220841	1			T23	95		T24	175		T25	1852
all_values[11]	12220841	1			T23	95		T24	175		T25	1852
all_values[12]	12220841	1			T23	95		T24	175		T25	1852
all_values[13]	12220841	1			T23	95		T24	175		T25	1852
all_values[14]	12220841	1			T23	95		T24	175		T25	1852
all_values[15]	12220841	1			T23	95		T24	175		T25	1852
all_values[16]	12220841	1			T23	95		T24	175		T25	1852
all_values[17]	12220841	1			T23	95		T24	175		T25	1852
all_values[18]	12220841	1			T23	95		T24	175		T25	1852
all_values[19]	12220841	1			T23	95		T24	175		T25	1852
all_values[20]	12220841	1			T23	95		T24	175		T25	1852
all_values[21]	12220841	1			T23	95		T24	175		T25	1852
all_values[22]	12220841	1			T23	95		T24	175		T25	1852
all_values[23]	12220841	1			T23	95		T24	175		T25	1852
all_values[24]	12220841	1			T23	95		T24	175		T25	1852
all_values[25]	12220841	1			T23	95		T24	175		T25	1852
all_values[26]	12220841	1			T23	95		T24	175		T25	1852
all_values[27]	12220841	1			T23	95		T24	175		T25	1852
all_values[28]	12220841	1			T23	95		T24	175		T25	1852
all_values[29]	12220841	1			T23	95		T24	175		T25	1852
all_values[30]	12220841	1			T23	95		T24	175		T25	1852
all_values[31]	12220841	1			T23	95		T24	175		T25	1852

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231314267

1

T23

3040

T24

5600

T25

30306

auto[1]

159752645

1

T25

28958

T28

13642

T29

186

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101865917

1

T23

3040

T24

5600

T25

7625

auto[1]

289200995

1

T25

51639

T28

24310

T29

285

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

386674133

1

T23

3040

T24

5600

T25

57131

auto[1]

4392779

1

T25

2133

T28

793

T29

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2696670	1			T23	95		T24	175		T25	186
all_values[0]	auto[0]	auto[0]	auto[1]	4471698	1			T25	764		T28	352		T29	9
all_values[0]	auto[0]	auto[1]	auto[0]	488345	1			T25	112		T28	50		T29	4
all_values[0]	auto[0]	auto[1]	auto[1]	4426944	1			T25	728		T28	380		T29	1
all_values[0]	auto[1]	auto[0]	auto[1]	68354	1			T25	39		T28	18		T29	1
all_values[0]	auto[1]	auto[1]	auto[1]	68830	1			T25	23		T28	12		T29	1
all_values[1]	auto[0]	auto[0]	auto[0]	2700324	1			T23	95		T24	175		T25	83
all_values[1]	auto[0]	auto[0]	auto[1]	4477638	1			T25	847		T28	475		T29	8
all_values[1]	auto[0]	auto[1]	auto[0]	487406	1			T25	97		T28	24		T32	142
all_values[1]	auto[0]	auto[1]	auto[1]	4418269	1			T25	758		T28	284		T29	6
all_values[1]	auto[1]	auto[0]	auto[1]	68811	1			T25	38		T28	14		T29	1
all_values[1]	auto[1]	auto[1]	auto[1]	68393	1			T25	29		T28	13		T1	30
all_values[2]	auto[0]	auto[0]	auto[0]	2693752	1			T23	95		T24	175		T25	228
all_values[2]	auto[0]	auto[0]	auto[1]	4529991	1			T25	828		T28	301		T29	4
all_values[2]	auto[0]	auto[1]	auto[0]	480417	1			T25	143		T28	87		T29	5
all_values[2]	auto[0]	auto[1]	auto[1]	4378943	1			T25	583		T28	350		T29	1
all_values[2]	auto[1]	auto[0]	auto[1]	69046	1			T25	42		T28	13		T29	1
all_values[2]	auto[1]	auto[1]	auto[1]	68692	1			T25	28		T28	15		T1	39
all_values[3]	auto[0]	auto[0]	auto[0]	2699298	1			T23	95		T24	175		T25	93
all_values[3]	auto[0]	auto[0]	auto[1]	4452615	1			T25	863		T28	297		T29	5
all_values[3]	auto[0]	auto[1]	auto[0]	484862	1			T25	81		T28	72		T29	10
all_values[3]	auto[0]	auto[1]	auto[1]	4447143	1			T25	756		T28	379		T29	2
all_values[3]	auto[1]	auto[0]	auto[1]	68714	1			T25	31		T28	17		T29	1
all_values[3]	auto[1]	auto[1]	auto[1]	68209	1			T25	28		T28	13		T1	42
all_values[4]	auto[0]	auto[0]	auto[0]	2700340	1			T23	95		T24	175		T25	114
all_values[4]	auto[0]	auto[0]	auto[1]	4468882	1			T25	749		T28	389		T29	7
all_values[4]	auto[0]	auto[1]	auto[0]	490903	1			T25	56		T28	34		T32	98
all_values[4]	auto[0]	auto[1]	auto[1]	4423604	1			T25	862		T28	337		T32	738
all_values[4]	auto[1]	auto[0]	auto[1]	68625	1			T25	33		T28	13		T29	1
all_values[4]	auto[1]	auto[1]	auto[1]	68487	1			T25	38		T28	14		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	2705304	1			T23	95		T24	175		T25	140
all_values[5]	auto[0]	auto[0]	auto[1]	4483733	1			T25	631		T28	420		T29	6
all_values[5]	auto[0]	auto[1]	auto[0]	487960	1			T25	121		T28	40		T29	3
all_values[5]	auto[0]	auto[1]	auto[1]	4406635	1			T25	895		T28	308		T29	8
all_values[5]	auto[1]	auto[0]	auto[1]	69125	1			T25	22		T28	12		T29	1
all_values[5]	auto[1]	auto[1]	auto[1]	68084	1			T25	43		T28	11		T29	1
all_values[6]	auto[0]	auto[0]	auto[0]	2693939	1			T23	95		T24	175		T25	157
all_values[6]	auto[0]	auto[0]	auto[1]	4442787	1			T25	873		T28	371		T29	7
all_values[6]	auto[0]	auto[1]	auto[0]	488598	1			T25	158		T28	21		T29	3
all_values[6]	auto[0]	auto[1]	auto[1]	4457885	1			T25	604		T28	382		T29	3
all_values[6]	auto[1]	auto[0]	auto[1]	69114	1			T25	37		T28	17		T29	1
all_values[6]	auto[1]	auto[1]	auto[1]	68518	1			T25	23		T28	7		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	2696158	1			T23	95		T24	175		T25	142
all_values[7]	auto[0]	auto[0]	auto[1]	4474355	1			T25	888		T28	411		T29	7
all_values[7]	auto[0]	auto[1]	auto[0]	481575	1			T25	56		T28	49		T32	75
all_values[7]	auto[0]	auto[1]	auto[1]	4431704	1			T25	696		T28	336		T32	683
all_values[7]	auto[1]	auto[0]	auto[1]	68791	1			T25	37		T28	13		T29	1
all_values[7]	auto[1]	auto[1]	auto[1]	68258	1			T25	33		T28	11		T33	1
all_values[8]	auto[0]	auto[0]	auto[0]	2700531	1			T23	95		T24	175		T25	146
all_values[8]	auto[0]	auto[0]	auto[1]	4442304	1			T25	580		T28	308		T29	6
all_values[8]	auto[0]	auto[1]	auto[0]	481975	1			T25	194		T28	25		T32	85
all_values[8]	auto[0]	auto[1]	auto[1]	4458852	1			T25	866		T28	460		T29	6
all_values[8]	auto[1]	auto[0]	auto[1]	69039	1			T25	24		T28	8		T29	1
all_values[8]	auto[1]	auto[1]	auto[1]	68140	1			T25	42		T28	12		T1	47
all_values[9]	auto[0]	auto[0]	auto[0]	2694556	1			T23	95		T24	175		T25	64
all_values[9]	auto[0]	auto[0]	auto[1]	4470520	1			T25	804		T28	294		T29	5
all_values[9]	auto[0]	auto[1]	auto[0]	479083	1			T25	94		T28	64		T29	6
all_values[9]	auto[0]	auto[1]	auto[1]	4439367	1			T25	820		T28	420		T32	627
all_values[9]	auto[1]	auto[0]	auto[1]	68589	1			T25	35		T28	10		T29	1
all_values[9]	auto[1]	auto[1]	auto[1]	68726	1			T25	35		T28	15		T33	1
all_values[10]	auto[0]	auto[0]	auto[0]	2690799	1			T23	95		T24	175		T25	100
all_values[10]	auto[0]	auto[0]	auto[1]	4464133	1			T25	664		T28	338		T29	9
all_values[10]	auto[0]	auto[1]	auto[0]	489149	1			T25	141		T28	94		T29	6
all_values[10]	auto[0]	auto[1]	auto[1]	4439668	1			T25	881		T28	336		T32	773
all_values[10]	auto[1]	auto[0]	auto[1]	69132	1			T25	30		T28	10		T33	1
all_values[10]	auto[1]	auto[1]	auto[1]	67960	1			T25	36		T28	15		T33	2
all_values[11]	auto[0]	auto[0]	auto[0]	2687942	1			T23	95		T24	175		T25	174
all_values[11]	auto[0]	auto[0]	auto[1]	4447900	1			T25	724		T28	302		T29	4
all_values[11]	auto[0]	auto[1]	auto[0]	480358	1			T25	82		T28	58		T32	34
all_values[11]	auto[0]	auto[1]	auto[1]	4467123	1			T25	807		T28	437		T32	710
all_values[11]	auto[1]	auto[0]	auto[1]	68334	1			T25	30		T28	11		T29	1
all_values[11]	auto[1]	auto[1]	auto[1]	69184	1			T25	35		T28	13		T33	1
all_values[12]	auto[0]	auto[0]	auto[0]	2698267	1			T23	95		T24	175		T25	134
all_values[12]	auto[0]	auto[0]	auto[1]	4473719	1			T25	743		T28	458		T29	2
all_values[12]	auto[0]	auto[1]	auto[0]	485313	1			T25	120		T28	50		T29	5
all_values[12]	auto[0]	auto[1]	auto[1]	4426552	1			T25	794		T28	231		T29	1
all_values[12]	auto[1]	auto[0]	auto[1]	68913	1			T25	29		T28	16		T29	2
all_values[12]	auto[1]	auto[1]	auto[1]	68077	1			T25	32		T28	6		T33	1
all_values[13]	auto[0]	auto[0]	auto[0]	2697977	1			T23	95		T24	175		T25	58
all_values[13]	auto[0]	auto[0]	auto[1]	4447694	1			T25	819		T28	413		T29	11
all_values[13]	auto[0]	auto[1]	auto[0]	485992	1			T25	140		T28	35		T29	4
all_values[13]	auto[0]	auto[1]	auto[1]	4451544	1			T25	768		T28	344		T29	1
all_values[13]	auto[1]	auto[0]	auto[1]	68702	1			T25	35		T28	9		T29	1
all_values[13]	auto[1]	auto[1]	auto[1]	68932	1			T25	32		T28	16		T29	1
all_values[14]	auto[0]	auto[0]	auto[0]	2690217	1			T23	95		T24	175		T25	138
all_values[14]	auto[0]	auto[0]	auto[1]	4442302	1			T25	807		T28	363		T29	10
all_values[14]	auto[0]	auto[1]	auto[0]	482018	1			T25	115		T28	59		T32	114
all_values[14]	auto[0]	auto[1]	auto[1]	4468784	1			T25	732		T28	350		T32	601
all_values[14]	auto[1]	auto[0]	auto[1]	68824	1			T25	35		T28	10		T33	2
all_values[14]	auto[1]	auto[1]	auto[1]	68696	1			T25	25		T28	11		T33	1
all_values[15]	auto[0]	auto[0]	auto[0]	2699523	1			T23	95		T24	175		T25	62
all_values[15]	auto[0]	auto[0]	auto[1]	4442741	1			T25	736		T28	269		T29	1
all_values[15]	auto[0]	auto[1]	auto[0]	491133	1			T25	138		T28	69		T29	10
all_values[15]	auto[0]	auto[1]	auto[1]	4450487	1			T25	846		T28	474		T29	2
all_values[15]	auto[1]	auto[0]	auto[1]	68446	1			T25	32		T28	9		T33	4
all_values[15]	auto[1]	auto[1]	auto[1]	68511	1			T25	38		T28	15		T1	42
all_values[16]	auto[0]	auto[0]	auto[0]	2699489	1			T23	95		T24	175		T25	165
all_values[16]	auto[0]	auto[0]	auto[1]	4485729	1			T25	768		T28	341		T29	3
all_values[16]	auto[0]	auto[1]	auto[0]	483128	1			T25	117		T28	69		T29	5
all_values[16]	auto[0]	auto[1]	auto[1]	4415203	1			T25	729		T28	402		T32	827
all_values[16]	auto[1]	auto[0]	auto[1]	69140	1			T25	31		T28	8		T33	5
all_values[16]	auto[1]	auto[1]	auto[1]	68152	1			T25	42		T28	12		T29	1
all_values[17]	auto[0]	auto[0]	auto[0]	2703453	1			T23	95		T24	175		T25	122
all_values[17]	auto[0]	auto[0]	auto[1]	4480724	1			T25	887		T28	365		T29	8
all_values[17]	auto[0]	auto[1]	auto[0]	477691	1			T25	130		T28	39		T32	147
all_values[17]	auto[0]	auto[1]	auto[1]	4421953	1			T25	645		T28	402		T29	6
all_values[17]	auto[1]	auto[0]	auto[1]	69281	1			T25	34		T28	11		T29	1
all_values[17]	auto[1]	auto[1]	auto[1]	67739	1			T25	34		T28	16		T1	37
all_values[18]	auto[0]	auto[0]	auto[0]	2699538	1			T23	95		T24	175		T25	119
all_values[18]	auto[0]	auto[0]	auto[1]	4471516	1			T25	946		T28	354		T32	949
all_values[18]	auto[0]	auto[1]	auto[0]	482298	1			T25	63		T28	43		T29	8
all_values[18]	auto[0]	auto[1]	auto[1]	4429912	1			T25	656		T28	427		T29	3
all_values[18]	auto[1]	auto[0]	auto[1]	68628	1			T25	47		T28	8		T1	31
all_values[18]	auto[1]	auto[1]	auto[1]	68949	1			T25	21		T28	8		T29	1
all_values[19]	auto[0]	auto[0]	auto[0]	2702204	1			T23	95		T24	175		T25	130
all_values[19]	auto[0]	auto[0]	auto[1]	4474518	1			T25	810		T28	474		T29	7
all_values[19]	auto[0]	auto[1]	auto[0]	482550	1			T25	171		T28	73		T32	60
all_values[19]	auto[0]	auto[1]	auto[1]	4423856	1			T25	669		T28	216		T32	767
all_values[19]	auto[1]	auto[0]	auto[1]	69235	1			T25	38		T28	14		T29	1
all_values[19]	auto[1]	auto[1]	auto[1]	68478	1			T25	34		T28	11		T33	2
all_values[20]	auto[0]	auto[0]	auto[0]	2699850	1			T23	95		T24	175		T25	112
all_values[20]	auto[0]	auto[0]	auto[1]	4466780	1			T25	698		T28	370		T29	6
all_values[20]	auto[0]	auto[1]	auto[0]	487242	1			T25	95		T28	40		T29	6
all_values[20]	auto[0]	auto[1]	auto[1]	4429719	1			T25	886		T28	372		T32	683
all_values[20]	auto[1]	auto[0]	auto[1]	69133	1			T25	25		T28	12		T29	1
all_values[20]	auto[1]	auto[1]	auto[1]	68117	1			T25	36		T28	11		T33	1
all_values[21]	auto[0]	auto[0]	auto[0]	2694562	1			T23	95		T24	175		T25	87
all_values[21]	auto[0]	auto[0]	auto[1]	4451517	1			T25	774		T28	405		T29	9
all_values[21]	auto[0]	auto[1]	auto[0]	487663	1			T25	124		T28	32		T32	61
all_values[21]	auto[0]	auto[1]	auto[1]	4449695	1			T25	802		T28	350		T29	6
all_values[21]	auto[1]	auto[0]	auto[1]	68975	1			T25	31		T28	10		T29	1
all_values[21]	auto[1]	auto[1]	auto[1]	68429	1			T25	34		T28	16		T1	33
all_values[22]	auto[0]	auto[0]	auto[0]	2700805	1			T23	95		T24	175		T25	106
all_values[22]	auto[0]	auto[0]	auto[1]	4447731	1			T25	861		T28	296		T29	9
all_values[22]	auto[0]	auto[1]	auto[0]	485295	1			T25	137		T28	22		T29	11
all_values[22]	auto[0]	auto[1]	auto[1]	4449600	1			T25	691		T28	478		T29	1
all_values[22]	auto[1]	auto[0]	auto[1]	69045	1			T25	35		T28	10		T33	3
all_values[22]	auto[1]	auto[1]	auto[1]	68365	1			T25	22		T28	13		T1	40
all_values[23]	auto[0]	auto[0]	auto[0]	2700185	1			T23	95		T24	175		T25	176
all_values[23]	auto[0]	auto[0]	auto[1]	4461027	1			T25	822		T28	340		T29	3
all_values[23]	auto[0]	auto[1]	auto[0]	488464	1			T25	166		T28	77		T29	9
all_values[23]	auto[0]	auto[1]	auto[1]	4433914	1			T25	613		T28	371		T29	2
all_values[23]	auto[1]	auto[0]	auto[1]	68958	1			T25	41		T28	10		T33	3
all_values[23]	auto[1]	auto[1]	auto[1]	68293	1			T25	34		T28	17		T29	1
all_values[24]	auto[0]	auto[0]	auto[0]	2697011	1			T23	95		T24	175		T25	109
all_values[24]	auto[0]	auto[0]	auto[1]	4454280	1			T25	933		T28	340		T29	8
all_values[24]	auto[0]	auto[1]	auto[0]	485844	1			T25	103		T28	23		T29	5
all_values[24]	auto[0]	auto[1]	auto[1]	4446388	1			T25	638		T28	431		T32	611
all_values[24]	auto[1]	auto[0]	auto[1]	68659	1			T25	37		T28	14		T29	1
all_values[24]	auto[1]	auto[1]	auto[1]	68659	1			T25	32		T28	14		T29	1
all_values[25]	auto[0]	auto[0]	auto[0]	2695580	1			T23	95		T24	175		T25	85
all_values[25]	auto[0]	auto[0]	auto[1]	4465442	1			T25	536		T28	313		T29	5
all_values[25]	auto[0]	auto[1]	auto[0]	486449	1			T25	103		T28	59		T32	47
all_values[25]	auto[0]	auto[1]	auto[1]	4436366	1			T25	1061		T28	395		T32	532
all_values[25]	auto[1]	auto[0]	auto[1]	68873	1			T25	26		T28	17		T29	1
all_values[25]	auto[1]	auto[1]	auto[1]	68131	1			T25	41		T28	15		T33	2
all_values[26]	auto[0]	auto[0]	auto[0]	2694433	1			T23	95		T24	175		T25	105
all_values[26]	auto[0]	auto[0]	auto[1]	4448289	1			T25	855		T28	319		T29	11
all_values[26]	auto[0]	auto[1]	auto[0]	486244	1			T25	46		T28	30		T29	4
all_values[26]	auto[0]	auto[1]	auto[1]	4454856	1			T25	782		T28	464		T29	1
all_values[26]	auto[1]	auto[0]	auto[1]	68360	1			T25	39		T28	11		T29	1
all_values[26]	auto[1]	auto[1]	auto[1]	68659	1			T25	25		T28	8		T29	1
all_values[27]	auto[0]	auto[0]	auto[0]	2694406	1			T23	95		T24	175		T25	155
all_values[27]	auto[0]	auto[0]	auto[1]	4444188	1			T25	823		T28	373		T29	9
all_values[27]	auto[0]	auto[1]	auto[0]	487982	1			T25	81		T28	27		T32	69
all_values[27]	auto[0]	auto[1]	auto[1]	4456959	1			T25	726		T28	364		T32	728
all_values[27]	auto[1]	auto[0]	auto[1]	68886	1			T25	38		T28	12		T29	1
all_values[27]	auto[1]	auto[1]	auto[1]	68420	1			T25	29		T28	13		T1	45
all_values[28]	auto[0]	auto[0]	auto[0]	2704200	1			T23	95		T24	175		T25	125
all_values[28]	auto[0]	auto[0]	auto[1]	4445814	1			T25	835		T28	459		T29	2
all_values[28]	auto[0]	auto[1]	auto[0]	484867	1			T25	104		T28	4		T29	11
all_values[28]	auto[0]	auto[1]	auto[1]	4448845	1			T25	720		T28	293		T32	729
all_values[28]	auto[1]	auto[0]	auto[1]	68666	1			T25	31		T28	18		T33	4
all_values[28]	auto[1]	auto[1]	auto[1]	68449	1			T25	37		T28	7		T29	1
all_values[29]	auto[0]	auto[0]	auto[0]	2698985	1			T23	95		T24	175		T25	160
all_values[29]	auto[0]	auto[0]	auto[1]	4434128	1			T25	814		T28	354		T29	8
all_values[29]	auto[0]	auto[1]	auto[0]	492083	1			T25	121		T28	57		T32	158
all_values[29]	auto[0]	auto[1]	auto[1]	4458459	1			T25	687		T28	388		T32	660
all_values[29]	auto[1]	auto[0]	auto[1]	68736	1			T25	41		T28	12		T33	2
all_values[29]	auto[1]	auto[1]	auto[1]	68450	1			T25	29		T28	15		T33	1
all_values[30]	auto[0]	auto[0]	auto[0]	2701484	1			T23	95		T24	175		T25	103
all_values[30]	auto[0]	auto[0]	auto[1]	4457984	1			T25	716		T28	494		T29	4
all_values[30]	auto[0]	auto[1]	auto[0]	485481	1			T25	123		T28	46		T29	4
all_values[30]	auto[0]	auto[1]	auto[1]	4438482	1			T25	841		T28	237		T29	7
all_values[30]	auto[1]	auto[0]	auto[1]	68968	1			T25	33		T28	15		T29	1
all_values[30]	auto[1]	auto[1]	auto[1]	68442	1			T25	36		T28	8		T29	1
all_values[31]	auto[0]	auto[0]	auto[0]	2703713	1			T23	95		T24	175		T25	148
all_values[31]	auto[0]	auto[0]	auto[1]	4453339	1			T25	787		T28	412		T29	2
all_values[31]	auto[0]	auto[1]	auto[0]	482054	1			T25	67		T28	30		T32	111
all_values[31]	auto[0]	auto[1]	auto[1]	4444487	1			T25	779		T28	349		T32	890
all_values[31]	auto[1]	auto[0]	auto[1]	68652	1			T25	39		T28	18		T33	6
all_values[31]	auto[1]	auto[1]	auto[1]	68596	1			T25	32		T28	10		T1	37

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal