Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[1]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[2]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[3]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[4]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[5]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[6]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[7]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[8]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[9]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[10]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[11]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[12]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[13]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[14]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[15]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[16]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[17]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[18]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[19]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[20]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[21]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[22]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[23]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[24]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[25]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[26]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[27]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[28]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[29]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[30]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[31]	12102881	1			T23	173		T24	331		T25	1740

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227254780

1

T23

1199

T24

8317

T25

42716

auto[1]

160037412

1

T23

4337

T24

2275

T25

12964

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310319295

1

T23

5090

T24

7758

T25

31922

auto[1]

76972897

1

T23

446

T24

2834

T25

23758

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

288312597

1

T23

3507

T24

5289

T25

28042

auto[1]

98979595

1

T23

2029

T24

5303

T25

27638

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4431715	1			T23	15		T24	118		T25	589
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3357818	1			T23	96		T24	10		T25	19
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1212557	1			T23	6		T24	87		T25	322
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1465692	1			T23	9		T24	83		T25	463
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	435088	1			T23	43		T24	7		T25	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1200011	1			T23	4		T24	26		T25	338
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4433905	1			T23	19		T24	133		T25	484
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3369397	1			T23	108		T24	17		T25	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1214457	1			T23	8		T24	69		T25	415
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1455653	1			T23	8		T24	68		T25	458
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	433791	1			T23	24		T24	4		T25	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1195678	1			T23	6		T24	40		T25	356
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4421427	1			T23	19		T24	114		T25	498
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3375873	1			T23	60		T24	21		T25	11
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1209065	1			T23	8		T24	53		T25	408
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1458641	1			T23	12		T24	82		T25	479
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	435949	1			T23	68		T24	8		T25	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1201926	1			T23	6		T24	53		T25	330
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4433747	1			T23	13		T24	163		T25	414
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3360860	1			T23	80		T24	16		T25	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1213937	1			T23	2		T24	49		T25	464
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1460059	1			T23	10		T24	47		T25	431
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	433947	1			T23	68		T24	10		T25	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1200331	1			T24	46		T25	406		T26	41
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4442730	1			T23	12		T24	122		T25	476
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3357090	1			T23	75		T24	18		T25	23
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1213402	1			T23	10		T24	52		T25	345
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1454747	1			T23	12		T24	88		T25	388
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	435566	1			T23	60		T24	11		T25	25
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1199346	1			T23	4		T24	40		T25	483
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4423801	1			T23	15		T24	129		T25	536
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3370979	1			T23	39		T24	10		T25	35
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1213327	1			T23	2		T24	35		T25	394
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1457730	1			T23	20		T24	99		T25	418
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	433045	1			T23	89		T24	13		T25	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1203999	1			T23	8		T24	45		T25	349
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4428908	1			T23	21		T24	55		T25	443
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3371888	1			T23	73		T24	2		T25	22
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1208680	1			T23	4		T24	20		T25	303
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1457646	1			T23	12		T24	168		T25	564
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	434185	1			T23	53		T24	20		T25	10
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1201574	1			T23	10		T24	66		T25	398
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4427550	1			T23	25		T24	104		T25	516
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3370312	1			T23	98		T24	16		T25	17
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1212348	1			T23	4		T24	52		T25	407
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1464618	1			T23	4		T24	107		T25	395
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	433069	1			T23	40		T24	12		T25	19
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1194984	1			T23	2		T24	40		T25	386
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4431375	1			T23	19		T24	145		T25	539
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3367982	1			T23	80		T24	13		T25	12
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1210843	1			T23	10		T24	14		T25	308
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1461545	1			T23	11		T24	110		T25	517
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	432080	1			T23	47		T24	9		T25	26
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1199056	1			T23	6		T24	40		T25	338
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4429418	1			T23	20		T24	70		T25	468
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3374131	1			T23	72		T24	7		T25	16
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1209108	1			T23	10		T24	32		T25	387
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1460419	1			T23	9		T24	155		T25	535
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	434522	1			T23	60		T24	16		T25	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1195283	1			T23	2		T24	51		T25	323
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4440457	1			T23	23		T24	122		T25	502
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3359980	1			T23	101		T24	18		T25	13
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1208886	1			T23	15		T24	51		T25	344
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1456026	1			T23	8		T24	86		T25	514
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	437045	1			T23	24		T24	8		T25	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1200487	1			T23	2		T24	46		T25	351
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4421894	1			T23	26		T24	84		T25	588
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3369777	1			T23	87		T24	4		T25	20
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1210139	1			T23	6		T24	33		T25	288
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1466630	1			T23	11		T24	130		T25	481
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	434230	1			T23	40		T24	21		T25	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1200211	1			T23	3		T24	59		T25	353
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4421544	1			T23	12		T24	124		T25	497
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3378115	1			T23	58		T24	16		T25	12
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1211700	1			T23	4		T24	51		T25	498
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1459270	1			T23	11		T24	102		T25	404
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	432220	1			T23	78		T24	12		T25	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1200032	1			T23	10		T24	26		T25	318
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4421474	1			T23	20		T24	120		T25	454
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3381371	1			T23	88		T24	10		T25	11
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1210400	1			T23	12		T24	18		T25	287
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1455381	1			T23	12		T24	116		T25	567
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	433776	1			T23	36		T24	19		T25	24
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1200479	1			T23	5		T24	48		T25	397
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4424015	1			T23	16		T24	153		T25	465
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3379071	1			T23	66		T24	14		T25	14
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1211187	1			T23	2		T24	20		T25	329
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1460040	1			T23	20		T24	101		T25	538
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	433447	1			T23	59		T24	16		T25	15
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1195121	1			T23	10		T24	27		T25	379
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4436380	1			T23	14		T24	104		T25	581
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3362167	1			T23	72		T24	14		T25	30
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1211884	1			T23	6		T24	55		T25	411
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1457265	1			T23	7		T24	67		T25	363
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	430503	1			T23	64		T24	17		T25	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1204682	1			T23	10		T24	74		T25	347
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4425014	1			T23	27		T24	141		T25	449
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3377764	1			T23	100		T24	18		T25	16
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1206851	1			T23	19		T24	36		T25	284
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1463590	1			T24	113		T25	538		T26	170
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	432574	1			T23	25		T24	7		T25	20
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1197088	1			T23	2		T24	16		T25	433
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4441647	1			T23	16		T24	136		T25	394
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3366899	1			T23	64		T24	14		T25	7
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1207136	1			T23	12		T24	32		T25	372
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1464668	1			T23	15		T24	104		T25	560
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	432755	1			T23	64		T24	9		T25	17
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1189776	1			T23	2		T24	36		T25	390
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4440598	1			T23	24		T24	134		T25	529
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3365735	1			T23	112		T24	19		T25	15
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1209630	1			T23	14		T24	35		T25	463
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1462810	1			T23	4		T24	92		T25	460
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	431711	1			T23	19		T24	9		T25	16
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1192397	1			T24	42		T25	257		T26	68
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4428814	1			T23	34		T24	107		T25	486
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3373387	1			T23	114		T24	5		T25	8
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1205813	1			T23	12		T24	16		T25	468
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1461789	1			T23	1		T24	129		T25	424
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	436804	1			T23	10		T24	20		T25	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1196274	1			T23	2		T24	54		T25	336
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4427432	1			T23	9		T24	118		T25	455
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3375406	1			T23	58		T24	18		T25	27
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1205053	1			T23	4		T24	37		T25	362
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1464983	1			T23	17		T24	113		T25	526
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	438321	1			T23	70		T24	11		T25	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1191686	1			T23	15		T24	34		T25	360
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4433483	1			T23	16		T24	120		T25	498
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3372204	1			T23	101		T24	10		T25	28
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1207270	1			T23	18		T24	64		T25	362
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1462079	1			T23	10		T24	102		T25	516
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	433315	1			T23	26		T24	14		T25	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1194530	1			T23	2		T24	21		T25	328
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4435168	1			T23	19		T24	103		T25	512
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3368255	1			T23	96		T24	9		T25	18
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1203275	1			T23	8		T24	52		T25	295
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1467171	1			T23	7		T24	96		T25	529
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	434949	1			T23	39		T24	14		T25	16
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1194063	1			T23	4		T24	57		T25	370
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4435565	1			T23	16		T24	40		T25	488
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3365470	1			T23	80		T24	13		T25	20
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1201726	1			T23	13		T24	32		T25	470
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1471532	1			T23	7		T24	168		T25	337
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	435941	1			T23	51		T24	21		T25	20
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1192647	1			T23	6		T24	57		T25	405
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4428043	1			T23	21		T24	92		T25	472
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3373717	1			T23	78		T24	14		T25	22
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1205150	1			T23	6		T24	57		T25	370
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1466461	1			T23	10		T24	117		T25	436
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	435656	1			T23	50		T24	11		T25	17
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1193854	1			T23	8		T24	40		T25	423
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4437072	1			T23	14		T24	102		T25	399
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3366183	1			T23	97		T24	14		T25	8
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1203891	1			T23	13		T24	60		T25	431
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1468773	1			T23	6		T24	86		T25	487
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	433469	1			T23	37		T24	11		T25	23
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1193493	1			T23	6		T24	58		T25	392
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4432233	1			T23	18		T24	75		T25	571
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3374945	1			T23	100		T24	11		T25	23
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1201705	1			T23	12		T24	55		T25	319
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1465766	1			T23	3		T24	117		T25	462
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	435142	1			T23	40		T24	25		T25	18
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1193090	1			T24	48		T25	347		T26	57
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4428373	1			T23	21		T24	89		T25	459
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3372012	1			T23	71		T24	11		T25	23
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1203149	1			T23	10		T24	8		T25	406
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1465365	1			T23	14		T24	132		T25	525
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	437061	1			T23	49		T24	20		T25	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1196921	1			T23	8		T24	71		T25	314
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4433985	1			T23	16		T24	96		T25	567
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3370621	1			T23	102		T24	13		T25	27
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1206872	1			T23	8		T24	40		T25	371
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1462360	1			T23	7		T24	117		T25	400
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	433198	1			T23	36		T24	12		T25	14
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1195845	1			T23	4		T24	53		T25	361
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4429312	1			T23	24		T24	100		T25	442
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3374026	1			T23	91		T24	9		T25	19
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1207693	1			T23	20		T24	68		T25	337
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1463043	1			T23	9		T24	96		T25	495
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	434012	1			T23	29		T24	13		T25	22
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1194795	1			T24	45		T25	425		T26	41
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4439767	1			T23	18		T24	114		T25	463
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3367179	1			T23	65		T24	7		T25	23
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1206107	1			T23	6		T24	38		T25	287
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1461592	1			T23	9		T24	109		T25	541
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	434349	1			T23	70		T24	15		T25	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1193887	1			T23	5		T24	48		T25	413
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4434106	1			T23	10		T24	72		T25	359
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3369536	1			T23	45		T24	10		T25	12
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1208254	1			T23	4		T24	68		T25	359
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1458989	1			T23	24		T24	129		T25	506
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	434140	1			T23	84		T24	14		T25	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1197856	1			T23	6		T24	38		T25	486

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal