Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[1]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[2]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[3]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[4]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[5]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[6]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[7]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[8]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[9]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[10]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[11]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[12]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[13]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[14]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[15]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[16]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[17]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[18]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[19]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[20]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[21]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[22]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[23]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[24]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[25]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[26]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[27]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[28]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[29]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[30]	12102881	1			T23	173		T24	331		T25	1740
bins_for_gpio_bits[31]	12102881	1			T23	173		T24	331		T25	1740

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227254780

1

T23

1199

T24

8317

T25

42716

auto[1]

160037412

1

T23

4337

T24

2275

T25

12964

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227247806

1

T23

1199

T24

8306

T25

42710

auto[1]

160044386

1

T23

4337

T24

2286

T25

12970

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6895041	1			T23	27		T24	284		T25	1321
bins_for_gpio_bits[0]	auto[0]	auto[1]	214684	1			T23	3		T24	4		T25	52
bins_for_gpio_bits[0]	auto[1]	auto[0]	214923	1			T23	3		T24	4		T25	53
bins_for_gpio_bits[0]	auto[1]	auto[1]	4778233	1			T23	140		T24	39		T25	314
bins_for_gpio_bits[1]	auto[0]	auto[0]	6889695	1			T23	31		T24	264		T25	1305
bins_for_gpio_bits[1]	auto[0]	auto[1]	214075	1			T23	4		T24	5		T25	51
bins_for_gpio_bits[1]	auto[1]	auto[0]	214320	1			T23	4		T24	6		T25	52
bins_for_gpio_bits[1]	auto[1]	auto[1]	4784791	1			T23	134		T24	56		T25	332
bins_for_gpio_bits[2]	auto[0]	auto[0]	6874168	1			T23	35		T24	241		T25	1334
bins_for_gpio_bits[2]	auto[0]	auto[1]	214754	1			T23	4		T24	8		T25	51
bins_for_gpio_bits[2]	auto[1]	auto[0]	214965	1			T23	4		T24	8		T25	51
bins_for_gpio_bits[2]	auto[1]	auto[1]	4798994	1			T23	130		T24	74		T25	304
bins_for_gpio_bits[3]	auto[0]	auto[0]	6893108	1			T23	24		T24	253		T25	1247
bins_for_gpio_bits[3]	auto[0]	auto[1]	214418	1			T23	1		T24	6		T25	62
bins_for_gpio_bits[3]	auto[1]	auto[0]	214635	1			T23	1		T24	6		T25	62
bins_for_gpio_bits[3]	auto[1]	auto[1]	4780720	1			T23	147		T24	66		T25	369
bins_for_gpio_bits[4]	auto[0]	auto[0]	6896472	1			T23	30		T24	256		T25	1154
bins_for_gpio_bits[4]	auto[0]	auto[1]	214216	1			T23	4		T24	5		T25	55
bins_for_gpio_bits[4]	auto[1]	auto[0]	214407	1			T23	4		T24	6		T25	55
bins_for_gpio_bits[4]	auto[1]	auto[1]	4777786	1			T23	135		T24	64		T25	476
bins_for_gpio_bits[5]	auto[0]	auto[0]	6879598	1			T23	36		T24	254		T25	1299
bins_for_gpio_bits[5]	auto[0]	auto[1]	215014	1			T23	1		T24	9		T25	49
bins_for_gpio_bits[5]	auto[1]	auto[0]	215260	1			T23	1		T24	9		T25	49
bins_for_gpio_bits[5]	auto[1]	auto[1]	4793009	1			T23	135		T24	59		T25	343
bins_for_gpio_bits[6]	auto[0]	auto[0]	6880946	1			T23	35		T24	234		T25	1257
bins_for_gpio_bits[6]	auto[0]	auto[1]	214051	1			T23	2		T24	9		T25	53
bins_for_gpio_bits[6]	auto[1]	auto[0]	214288	1			T23	2		T24	9		T25	53
bins_for_gpio_bits[6]	auto[1]	auto[1]	4793596	1			T23	134		T24	79		T25	377
bins_for_gpio_bits[7]	auto[0]	auto[0]	6890140	1			T23	31		T24	254		T25	1265
bins_for_gpio_bits[7]	auto[0]	auto[1]	214153	1			T23	2		T24	8		T25	53
bins_for_gpio_bits[7]	auto[1]	auto[0]	214376	1			T23	2		T24	9		T25	53
bins_for_gpio_bits[7]	auto[1]	auto[1]	4784212	1			T23	138		T24	60		T25	369
bins_for_gpio_bits[8]	auto[0]	auto[0]	6889231	1			T23	36		T24	263		T25	1313
bins_for_gpio_bits[8]	auto[0]	auto[1]	214340	1			T23	4		T24	6		T25	51
bins_for_gpio_bits[8]	auto[1]	auto[0]	214532	1			T23	4		T24	6		T25	51
bins_for_gpio_bits[8]	auto[1]	auto[1]	4784778	1			T23	129		T24	56		T25	325
bins_for_gpio_bits[9]	auto[0]	auto[0]	6884915	1			T23	35		T24	246		T25	1336
bins_for_gpio_bits[9]	auto[0]	auto[1]	213843	1			T23	4		T24	10		T25	54
bins_for_gpio_bits[9]	auto[1]	auto[0]	214030	1			T23	4		T24	11		T25	54
bins_for_gpio_bits[9]	auto[1]	auto[1]	4790093	1			T23	130		T24	64		T25	296
bins_for_gpio_bits[10]	auto[0]	auto[0]	6890929	1			T23	41		T24	250		T25	1305
bins_for_gpio_bits[10]	auto[0]	auto[1]	214220	1			T23	5		T24	9		T25	54
bins_for_gpio_bits[10]	auto[1]	auto[0]	214440	1			T23	5		T24	9		T25	55
bins_for_gpio_bits[10]	auto[1]	auto[1]	4783292	1			T23	122		T24	63		T25	326
bins_for_gpio_bits[11]	auto[0]	auto[0]	6883364	1			T23	40		T24	239		T25	1304
bins_for_gpio_bits[11]	auto[0]	auto[1]	215108	1			T23	3		T24	7		T25	53
bins_for_gpio_bits[11]	auto[1]	auto[0]	215299	1			T23	3		T24	8		T25	53
bins_for_gpio_bits[11]	auto[1]	auto[1]	4789110	1			T23	127		T24	77		T25	330
bins_for_gpio_bits[12]	auto[0]	auto[0]	6877666	1			T23	25		T24	274		T25	1346
bins_for_gpio_bits[12]	auto[0]	auto[1]	214646	1			T23	2		T24	2		T25	53
bins_for_gpio_bits[12]	auto[1]	auto[0]	214848	1			T23	2		T24	3		T25	53
bins_for_gpio_bits[12]	auto[1]	auto[1]	4795721	1			T23	144		T24	52		T25	288
bins_for_gpio_bits[13]	auto[0]	auto[0]	6872564	1			T23	40		T24	249		T25	1249
bins_for_gpio_bits[13]	auto[0]	auto[1]	214473	1			T23	4		T24	5		T25	59
bins_for_gpio_bits[13]	auto[1]	auto[0]	214691	1			T23	4		T24	5		T25	59
bins_for_gpio_bits[13]	auto[1]	auto[1]	4801153	1			T23	125		T24	72		T25	373
bins_for_gpio_bits[14]	auto[0]	auto[0]	6881108	1			T23	37		T24	270		T25	1274
bins_for_gpio_bits[14]	auto[0]	auto[1]	213910	1			T23	1		T24	4		T25	58
bins_for_gpio_bits[14]	auto[1]	auto[0]	214134	1			T23	1		T24	4		T25	58
bins_for_gpio_bits[14]	auto[1]	auto[1]	4793729	1			T23	134		T24	53		T25	350
bins_for_gpio_bits[15]	auto[0]	auto[0]	6890894	1			T23	24		T24	217		T25	1308
bins_for_gpio_bits[15]	auto[0]	auto[1]	214416	1			T23	3		T24	8		T25	47
bins_for_gpio_bits[15]	auto[1]	auto[0]	214635	1			T23	3		T24	9		T25	47
bins_for_gpio_bits[15]	auto[1]	auto[1]	4782936	1			T23	143		T24	97		T25	338
bins_for_gpio_bits[16]	auto[0]	auto[0]	6880284	1			T23	40		T24	287		T25	1217
bins_for_gpio_bits[16]	auto[0]	auto[1]	214979	1			T23	6		T24	3		T25	54
bins_for_gpio_bits[16]	auto[1]	auto[0]	215171	1			T23	6		T24	3		T25	54
bins_for_gpio_bits[16]	auto[1]	auto[1]	4792447	1			T23	121		T24	38		T25	415
bins_for_gpio_bits[17]	auto[0]	auto[0]	6898957	1			T23	39		T24	265		T25	1266
bins_for_gpio_bits[17]	auto[0]	auto[1]	214270	1			T23	4		T24	7		T25	60
bins_for_gpio_bits[17]	auto[1]	auto[0]	214494	1			T23	4		T24	7		T25	60
bins_for_gpio_bits[17]	auto[1]	auto[1]	4775160	1			T23	126		T24	52		T25	354
bins_for_gpio_bits[18]	auto[0]	auto[0]	6898086	1			T23	35		T24	256		T25	1408
bins_for_gpio_bits[18]	auto[0]	auto[1]	214725	1			T23	7		T24	5		T25	44
bins_for_gpio_bits[18]	auto[1]	auto[0]	214952	1			T23	7		T24	5		T25	44
bins_for_gpio_bits[18]	auto[1]	auto[1]	4775118	1			T23	124		T24	65		T25	244
bins_for_gpio_bits[19]	auto[0]	auto[0]	6881617	1			T23	41		T24	243		T25	1328
bins_for_gpio_bits[19]	auto[0]	auto[1]	214532	1			T23	6		T24	9		T25	50
bins_for_gpio_bits[19]	auto[1]	auto[0]	214799	1			T23	6		T24	9		T25	50
bins_for_gpio_bits[19]	auto[1]	auto[1]	4791933	1			T23	120		T24	70		T25	312
bins_for_gpio_bits[20]	auto[0]	auto[0]	6883085	1			T23	28		T24	260		T25	1288
bins_for_gpio_bits[20]	auto[0]	auto[1]	214161	1			T23	2		T24	7		T25	55
bins_for_gpio_bits[20]	auto[1]	auto[0]	214383	1			T23	2		T24	8		T25	55
bins_for_gpio_bits[20]	auto[1]	auto[1]	4791252	1			T23	141		T24	56		T25	342
bins_for_gpio_bits[21]	auto[0]	auto[0]	6888197	1			T23	38		T24	279		T25	1330
bins_for_gpio_bits[21]	auto[0]	auto[1]	214403	1			T23	6		T24	7		T25	45
bins_for_gpio_bits[21]	auto[1]	auto[0]	214635	1			T23	6		T24	7		T25	46
bins_for_gpio_bits[21]	auto[1]	auto[1]	4785646	1			T23	123		T24	38		T25	319
bins_for_gpio_bits[22]	auto[0]	auto[0]	6890856	1			T23	31		T24	241		T25	1286
bins_for_gpio_bits[22]	auto[0]	auto[1]	214551	1			T23	3		T24	10		T25	50
bins_for_gpio_bits[22]	auto[1]	auto[0]	214758	1			T23	3		T24	10		T25	50
bins_for_gpio_bits[22]	auto[1]	auto[1]	4782716	1			T23	136		T24	70		T25	354
bins_for_gpio_bits[23]	auto[0]	auto[0]	6894457	1			T23	31		T24	229		T25	1234
bins_for_gpio_bits[23]	auto[0]	auto[1]	214169	1			T23	5		T24	11		T25	60
bins_for_gpio_bits[23]	auto[1]	auto[0]	214366	1			T23	5		T24	11		T25	61
bins_for_gpio_bits[23]	auto[1]	auto[1]	4779889	1			T23	132		T24	80		T25	385
bins_for_gpio_bits[24]	auto[0]	auto[0]	6884833	1			T23	35		T24	256		T25	1226
bins_for_gpio_bits[24]	auto[0]	auto[1]	214561	1			T23	2		T24	10		T25	51
bins_for_gpio_bits[24]	auto[1]	auto[0]	214821	1			T23	2		T24	10		T25	52
bins_for_gpio_bits[24]	auto[1]	auto[1]	4788666	1			T23	134		T24	55		T25	411
bins_for_gpio_bits[25]	auto[0]	auto[0]	6894857	1			T23	29		T24	238		T25	1259
bins_for_gpio_bits[25]	auto[0]	auto[1]	214673	1			T23	4		T24	10		T25	58
bins_for_gpio_bits[25]	auto[1]	auto[0]	214879	1			T23	4		T24	10		T25	58
bins_for_gpio_bits[25]	auto[1]	auto[1]	4778472	1			T23	136		T24	73		T25	365
bins_for_gpio_bits[26]	auto[0]	auto[0]	6885453	1			T23	28		T24	236		T25	1304
bins_for_gpio_bits[26]	auto[0]	auto[1]	214065	1			T23	5		T24	11		T25	48
bins_for_gpio_bits[26]	auto[1]	auto[0]	214251	1			T23	5		T24	11		T25	48
bins_for_gpio_bits[26]	auto[1]	auto[1]	4789112	1			T23	135		T24	73		T25	340
bins_for_gpio_bits[27]	auto[0]	auto[0]	6882172	1			T23	41		T24	220		T25	1345
bins_for_gpio_bits[27]	auto[0]	auto[1]	214523	1			T23	4		T24	8		T25	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	214715	1			T23	4		T24	9		T25	45
bins_for_gpio_bits[27]	auto[1]	auto[1]	4791471	1			T23	124		T24	94		T25	305
bins_for_gpio_bits[28]	auto[0]	auto[0]	6888119	1			T23	27		T24	241		T25	1291
bins_for_gpio_bits[28]	auto[0]	auto[1]	214829	1			T23	4		T24	11		T25	47
bins_for_gpio_bits[28]	auto[1]	auto[0]	215098	1			T23	4		T24	12		T25	47
bins_for_gpio_bits[28]	auto[1]	auto[1]	4784835	1			T23	138		T24	67		T25	355
bins_for_gpio_bits[29]	auto[0]	auto[0]	6885045	1			T23	45		T24	255		T25	1218
bins_for_gpio_bits[29]	auto[0]	auto[1]	214814	1			T23	8		T24	9		T25	56
bins_for_gpio_bits[29]	auto[1]	auto[0]	215003	1			T23	8		T24	9		T25	56
bins_for_gpio_bits[29]	auto[1]	auto[1]	4788019	1			T23	112		T24	58		T25	410
bins_for_gpio_bits[30]	auto[0]	auto[0]	6892686	1			T23	30		T24	252		T25	1233
bins_for_gpio_bits[30]	auto[0]	auto[1]	214585	1			T23	3		T24	9		T25	58
bins_for_gpio_bits[30]	auto[1]	auto[0]	214780	1			T23	3		T24	9		T25	58
bins_for_gpio_bits[30]	auto[1]	auto[1]	4780830	1			T23	137		T24	61		T25	391
bins_for_gpio_bits[31]	auto[0]	auto[0]	6886251	1			T23	36		T24	261		T25	1171
bins_for_gpio_bits[31]	auto[0]	auto[1]	214851	1			T23	2		T24	7		T25	53
bins_for_gpio_bits[31]	auto[1]	auto[0]	215098	1			T23	2		T24	8		T25	53
bins_for_gpio_bits[31]	auto[1]	auto[1]	4786681	1			T23	133		T24	55		T25	463