Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7236722 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
989 |
| auto[1] |
4984119 |
1 |
|
|
T25 |
863 |
|
T28 |
442 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11596614 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1816 |
| auto[1] |
624227 |
1 |
|
|
T25 |
36 |
|
T28 |
20 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7234140 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
907 |
| auto[1] |
4986701 |
1 |
|
|
T25 |
945 |
|
T28 |
436 |
|
T29 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2201219 |
1 |
|
|
T25 |
514 |
|
T28 |
199 |
|
T29 |
13 |
| auto[1] |
auto[0] |
auto[1] |
316086 |
1 |
|
|
T25 |
22 |
|
T28 |
11 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2161255 |
1 |
|
|
T25 |
395 |
|
T28 |
217 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
308141 |
1 |
|
|
T25 |
14 |
|
T28 |
9 |
|
T32 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7246773 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
968 |
| auto[1] |
4974068 |
1 |
|
|
T25 |
884 |
|
T28 |
321 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11600936 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1818 |
| auto[1] |
619905 |
1 |
|
|
T25 |
34 |
|
T28 |
23 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7257239 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
832 |
| auto[1] |
4963602 |
1 |
|
|
T25 |
1020 |
|
T28 |
468 |
|
T29 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2184195 |
1 |
|
|
T25 |
538 |
|
T28 |
253 |
|
T29 |
12 |
| auto[1] |
auto[0] |
auto[1] |
311555 |
1 |
|
|
T25 |
16 |
|
T28 |
12 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2159502 |
1 |
|
|
T25 |
448 |
|
T28 |
192 |
|
T32 |
239 |
| auto[1] |
auto[1] |
auto[1] |
308350 |
1 |
|
|
T25 |
18 |
|
T28 |
11 |
|
T32 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7224064 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
794 |
| auto[1] |
4996777 |
1 |
|
|
T25 |
1058 |
|
T28 |
445 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11587424 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1824 |
| auto[1] |
633417 |
1 |
|
|
T25 |
28 |
|
T28 |
15 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7188031 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1085 |
| auto[1] |
5032810 |
1 |
|
|
T25 |
767 |
|
T28 |
345 |
|
T29 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2201093 |
1 |
|
|
T25 |
260 |
|
T28 |
149 |
|
T29 |
10 |
| auto[1] |
auto[0] |
auto[1] |
317430 |
1 |
|
|
T25 |
7 |
|
T28 |
8 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2198300 |
1 |
|
|
T25 |
479 |
|
T28 |
181 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
315987 |
1 |
|
|
T25 |
21 |
|
T28 |
7 |
|
T32 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7204176 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
928 |
| auto[1] |
5016665 |
1 |
|
|
T25 |
924 |
|
T28 |
508 |
|
T32 |
744 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11591581 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1814 |
| auto[1] |
629260 |
1 |
|
|
T25 |
38 |
|
T28 |
22 |
|
T32 |
126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7205699 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
875 |
| auto[1] |
5015142 |
1 |
|
|
T25 |
977 |
|
T28 |
396 |
|
T29 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2189328 |
1 |
|
|
T25 |
503 |
|
T28 |
195 |
|
T29 |
17 |
| auto[1] |
auto[0] |
auto[1] |
314243 |
1 |
|
|
T25 |
15 |
|
T28 |
14 |
|
T32 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2196554 |
1 |
|
|
T25 |
436 |
|
T28 |
179 |
|
T32 |
300 |
| auto[1] |
auto[1] |
auto[1] |
315017 |
1 |
|
|
T25 |
23 |
|
T28 |
8 |
|
T32 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7240899 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
906 |
| auto[1] |
4979942 |
1 |
|
|
T25 |
946 |
|
T28 |
287 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11593344 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1819 |
| auto[1] |
627497 |
1 |
|
|
T25 |
33 |
|
T28 |
23 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7216732 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
955 |
| auto[1] |
5004109 |
1 |
|
|
T25 |
897 |
|
T28 |
444 |
|
T29 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2209873 |
1 |
|
|
T25 |
458 |
|
T28 |
289 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
316877 |
1 |
|
|
T25 |
16 |
|
T28 |
14 |
|
T32 |
62 |
| auto[1] |
auto[1] |
auto[0] |
2166739 |
1 |
|
|
T25 |
406 |
|
T28 |
132 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
310620 |
1 |
|
|
T25 |
17 |
|
T28 |
9 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7214373 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
912 |
| auto[1] |
5006468 |
1 |
|
|
T25 |
940 |
|
T28 |
395 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11599325 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1811 |
| auto[1] |
621516 |
1 |
|
|
T25 |
41 |
|
T28 |
23 |
|
T32 |
190 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7249619 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
855 |
| auto[1] |
4971222 |
1 |
|
|
T25 |
997 |
|
T28 |
443 |
|
T29 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2171319 |
1 |
|
|
T25 |
501 |
|
T28 |
220 |
|
T29 |
12 |
| auto[1] |
auto[0] |
auto[1] |
310753 |
1 |
|
|
T25 |
26 |
|
T28 |
12 |
|
T32 |
91 |
| auto[1] |
auto[1] |
auto[0] |
2178387 |
1 |
|
|
T25 |
455 |
|
T28 |
200 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
310763 |
1 |
|
|
T25 |
15 |
|
T28 |
11 |
|
T32 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7201343 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
980 |
| auto[1] |
5019498 |
1 |
|
|
T25 |
872 |
|
T28 |
420 |
|
T32 |
715 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11586202 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1821 |
| auto[1] |
634639 |
1 |
|
|
T25 |
31 |
|
T28 |
22 |
|
T32 |
98 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7167946 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
993 |
| auto[1] |
5052895 |
1 |
|
|
T25 |
859 |
|
T28 |
510 |
|
T29 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2199980 |
1 |
|
|
T25 |
427 |
|
T28 |
253 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
316179 |
1 |
|
|
T25 |
14 |
|
T28 |
11 |
|
T32 |
56 |
| auto[1] |
auto[1] |
auto[0] |
2218276 |
1 |
|
|
T25 |
401 |
|
T28 |
235 |
|
T32 |
186 |
| auto[1] |
auto[1] |
auto[1] |
318460 |
1 |
|
|
T25 |
17 |
|
T28 |
11 |
|
T32 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7210710 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
830 |
| auto[1] |
5010131 |
1 |
|
|
T25 |
1022 |
|
T28 |
558 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11599801 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1818 |
| auto[1] |
621040 |
1 |
|
|
T25 |
34 |
|
T28 |
17 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7256701 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1025 |
| auto[1] |
4964140 |
1 |
|
|
T25 |
827 |
|
T28 |
420 |
|
T29 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2174532 |
1 |
|
|
T25 |
391 |
|
T28 |
168 |
|
T29 |
4 |
| auto[1] |
auto[0] |
auto[1] |
310951 |
1 |
|
|
T25 |
13 |
|
T28 |
7 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2168568 |
1 |
|
|
T25 |
402 |
|
T28 |
235 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[1] |
310089 |
1 |
|
|
T25 |
21 |
|
T28 |
10 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7254358 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
964 |
| auto[1] |
4966483 |
1 |
|
|
T25 |
888 |
|
T28 |
483 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11593103 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1817 |
| auto[1] |
627738 |
1 |
|
|
T25 |
35 |
|
T28 |
18 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7210507 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
960 |
| auto[1] |
5010334 |
1 |
|
|
T25 |
892 |
|
T28 |
384 |
|
T29 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2213596 |
1 |
|
|
T25 |
477 |
|
T28 |
191 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
317182 |
1 |
|
|
T25 |
19 |
|
T28 |
6 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2169000 |
1 |
|
|
T25 |
380 |
|
T28 |
175 |
|
T32 |
350 |
| auto[1] |
auto[1] |
auto[1] |
310556 |
1 |
|
|
T25 |
16 |
|
T28 |
12 |
|
T32 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7253458 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1043 |
| auto[1] |
4967383 |
1 |
|
|
T25 |
809 |
|
T28 |
457 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11599333 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1821 |
| auto[1] |
621508 |
1 |
|
|
T25 |
31 |
|
T28 |
15 |
|
T32 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7252572 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1074 |
| auto[1] |
4968269 |
1 |
|
|
T25 |
778 |
|
T28 |
434 |
|
T29 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2190168 |
1 |
|
|
T25 |
452 |
|
T28 |
198 |
|
T29 |
18 |
| auto[1] |
auto[0] |
auto[1] |
312943 |
1 |
|
|
T25 |
19 |
|
T28 |
8 |
|
T32 |
52 |
| auto[1] |
auto[1] |
auto[0] |
2156593 |
1 |
|
|
T25 |
295 |
|
T28 |
221 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
308565 |
1 |
|
|
T25 |
12 |
|
T28 |
7 |
|
T32 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7239682 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1112 |
| auto[1] |
4981159 |
1 |
|
|
T25 |
740 |
|
T28 |
478 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11591815 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1828 |
| auto[1] |
629026 |
1 |
|
|
T25 |
24 |
|
T28 |
23 |
|
T32 |
157 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7211027 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1094 |
| auto[1] |
5009814 |
1 |
|
|
T25 |
758 |
|
T28 |
510 |
|
T29 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2205965 |
1 |
|
|
T25 |
431 |
|
T28 |
195 |
|
T29 |
2 |
| auto[1] |
auto[0] |
auto[1] |
317322 |
1 |
|
|
T25 |
16 |
|
T28 |
5 |
|
T32 |
98 |
| auto[1] |
auto[1] |
auto[0] |
2174823 |
1 |
|
|
T25 |
303 |
|
T28 |
292 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
311704 |
1 |
|
|
T25 |
8 |
|
T28 |
18 |
|
T32 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7245957 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
978 |
| auto[1] |
4974884 |
1 |
|
|
T25 |
874 |
|
T28 |
300 |
|
T32 |
827 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11593911 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1821 |
| auto[1] |
626930 |
1 |
|
|
T25 |
31 |
|
T28 |
15 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7216729 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
839 |
| auto[1] |
5004112 |
1 |
|
|
T25 |
1013 |
|
T28 |
456 |
|
T29 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2211022 |
1 |
|
|
T25 |
525 |
|
T28 |
285 |
|
T29 |
10 |
| auto[1] |
auto[0] |
auto[1] |
317486 |
1 |
|
|
T25 |
20 |
|
T28 |
8 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2166160 |
1 |
|
|
T25 |
457 |
|
T28 |
156 |
|
T32 |
347 |
| auto[1] |
auto[1] |
auto[1] |
309444 |
1 |
|
|
T25 |
11 |
|
T28 |
7 |
|
T32 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7292789 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1098 |
| auto[1] |
4928052 |
1 |
|
|
T25 |
754 |
|
T28 |
452 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11595584 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1822 |
| auto[1] |
625257 |
1 |
|
|
T25 |
30 |
|
T28 |
7 |
|
T32 |
167 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7232971 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
830 |
| auto[1] |
4987870 |
1 |
|
|
T25 |
1022 |
|
T28 |
258 |
|
T29 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2205553 |
1 |
|
|
T25 |
653 |
|
T28 |
99 |
|
T29 |
6 |
| auto[1] |
auto[0] |
auto[1] |
317868 |
1 |
|
|
T25 |
21 |
|
T28 |
5 |
|
T32 |
88 |
| auto[1] |
auto[1] |
auto[0] |
2157060 |
1 |
|
|
T25 |
339 |
|
T28 |
152 |
|
T32 |
301 |
| auto[1] |
auto[1] |
auto[1] |
307389 |
1 |
|
|
T25 |
9 |
|
T28 |
2 |
|
T32 |
79 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7235763 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
835 |
| auto[1] |
4985078 |
1 |
|
|
T25 |
1017 |
|
T28 |
423 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11592881 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1814 |
| auto[1] |
627960 |
1 |
|
|
T25 |
38 |
|
T28 |
10 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7207977 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
917 |
| auto[1] |
5012864 |
1 |
|
|
T25 |
935 |
|
T28 |
321 |
|
T29 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2199151 |
1 |
|
|
T25 |
318 |
|
T28 |
179 |
|
T29 |
13 |
| auto[1] |
auto[0] |
auto[1] |
314848 |
1 |
|
|
T25 |
15 |
|
T28 |
7 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2185753 |
1 |
|
|
T25 |
579 |
|
T28 |
132 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
313112 |
1 |
|
|
T25 |
23 |
|
T28 |
3 |
|
T32 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7215054 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
892 |
| auto[1] |
5005787 |
1 |
|
|
T25 |
960 |
|
T28 |
398 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11593114 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1826 |
| auto[1] |
627727 |
1 |
|
|
T25 |
26 |
|
T28 |
18 |
|
T32 |
181 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7216587 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1157 |
| auto[1] |
5004254 |
1 |
|
|
T25 |
695 |
|
T28 |
512 |
|
T29 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2185815 |
1 |
|
|
T25 |
322 |
|
T28 |
254 |
|
T29 |
10 |
| auto[1] |
auto[0] |
auto[1] |
313584 |
1 |
|
|
T25 |
12 |
|
T28 |
10 |
|
T32 |
98 |
| auto[1] |
auto[1] |
auto[0] |
2190712 |
1 |
|
|
T25 |
347 |
|
T28 |
240 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[1] |
314143 |
1 |
|
|
T25 |
14 |
|
T28 |
8 |
|
T32 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7217581 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1002 |
| auto[1] |
5003260 |
1 |
|
|
T25 |
850 |
|
T28 |
513 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11593898 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1825 |
| auto[1] |
626943 |
1 |
|
|
T25 |
27 |
|
T28 |
15 |
|
T32 |
196 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219712 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1071 |
| auto[1] |
5001129 |
1 |
|
|
T25 |
781 |
|
T28 |
464 |
|
T29 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2184881 |
1 |
|
|
T25 |
422 |
|
T28 |
203 |
|
T29 |
5 |
| auto[1] |
auto[0] |
auto[1] |
313508 |
1 |
|
|
T25 |
14 |
|
T28 |
8 |
|
T32 |
95 |
| auto[1] |
auto[1] |
auto[0] |
2189305 |
1 |
|
|
T25 |
332 |
|
T28 |
246 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[1] |
313435 |
1 |
|
|
T25 |
13 |
|
T28 |
7 |
|
T32 |
101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7230170 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1039 |
| auto[1] |
4990671 |
1 |
|
|
T25 |
813 |
|
T28 |
465 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11596066 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1814 |
| auto[1] |
624775 |
1 |
|
|
T25 |
38 |
|
T28 |
9 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7236162 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
953 |
| auto[1] |
4984679 |
1 |
|
|
T25 |
899 |
|
T28 |
386 |
|
T29 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2188421 |
1 |
|
|
T25 |
510 |
|
T28 |
176 |
|
T29 |
6 |
| auto[1] |
auto[0] |
auto[1] |
313599 |
1 |
|
|
T25 |
24 |
|
T28 |
3 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2171483 |
1 |
|
|
T25 |
351 |
|
T28 |
201 |
|
T29 |
10 |
| auto[1] |
auto[1] |
auto[1] |
311176 |
1 |
|
|
T25 |
14 |
|
T28 |
6 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219950 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1079 |
| auto[1] |
5000891 |
1 |
|
|
T25 |
773 |
|
T28 |
468 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11591129 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1818 |
| auto[1] |
629712 |
1 |
|
|
T25 |
34 |
|
T28 |
16 |
|
T32 |
163 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7204358 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1015 |
| auto[1] |
5016483 |
1 |
|
|
T25 |
837 |
|
T28 |
334 |
|
T29 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2193996 |
1 |
|
|
T25 |
471 |
|
T28 |
139 |
|
T29 |
6 |
| auto[1] |
auto[0] |
auto[1] |
315026 |
1 |
|
|
T25 |
19 |
|
T28 |
6 |
|
T32 |
83 |
| auto[1] |
auto[1] |
auto[0] |
2192775 |
1 |
|
|
T25 |
332 |
|
T28 |
179 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
314686 |
1 |
|
|
T25 |
15 |
|
T28 |
10 |
|
T32 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7229895 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
647 |
| auto[1] |
4990946 |
1 |
|
|
T25 |
1205 |
|
T28 |
469 |
|
T32 |
579 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11598384 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1811 |
| auto[1] |
622457 |
1 |
|
|
T25 |
41 |
|
T28 |
16 |
|
T32 |
169 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7238213 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
841 |
| auto[1] |
4982628 |
1 |
|
|
T25 |
1011 |
|
T28 |
378 |
|
T29 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2190351 |
1 |
|
|
T25 |
340 |
|
T28 |
148 |
|
T29 |
16 |
| auto[1] |
auto[0] |
auto[1] |
312607 |
1 |
|
|
T25 |
19 |
|
T28 |
8 |
|
T32 |
101 |
| auto[1] |
auto[1] |
auto[0] |
2169820 |
1 |
|
|
T25 |
630 |
|
T28 |
214 |
|
T32 |
287 |
| auto[1] |
auto[1] |
auto[1] |
309850 |
1 |
|
|
T25 |
22 |
|
T28 |
8 |
|
T32 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |