Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7258162 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
793 |
| auto[1] |
4962679 |
1 |
|
|
T25 |
1059 |
|
T28 |
359 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11591650 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1810 |
| auto[1] |
629191 |
1 |
|
|
T25 |
42 |
|
T28 |
20 |
|
T32 |
149 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7205557 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
776 |
| auto[1] |
5015284 |
1 |
|
|
T25 |
1076 |
|
T28 |
412 |
|
T29 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2218128 |
1 |
|
|
T25 |
396 |
|
T28 |
232 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
318511 |
1 |
|
|
T25 |
14 |
|
T28 |
14 |
|
T32 |
87 |
| auto[1] |
auto[1] |
auto[0] |
2167965 |
1 |
|
|
T25 |
638 |
|
T28 |
160 |
|
T32 |
262 |
| auto[1] |
auto[1] |
auto[1] |
310680 |
1 |
|
|
T25 |
28 |
|
T28 |
6 |
|
T32 |
62 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |