Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7205840 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1067 |
| auto[1] |
5015001 |
1 |
|
|
T25 |
785 |
|
T28 |
410 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11592195 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1818 |
| auto[1] |
628646 |
1 |
|
|
T25 |
34 |
|
T28 |
26 |
|
T32 |
148 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7204829 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1083 |
| auto[1] |
5016012 |
1 |
|
|
T25 |
769 |
|
T28 |
548 |
|
T29 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2177221 |
1 |
|
|
T25 |
449 |
|
T28 |
242 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
311659 |
1 |
|
|
T25 |
21 |
|
T28 |
12 |
|
T32 |
61 |
| auto[1] |
auto[1] |
auto[0] |
2210145 |
1 |
|
|
T25 |
286 |
|
T28 |
280 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[1] |
316987 |
1 |
|
|
T25 |
13 |
|
T28 |
14 |
|
T32 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |