Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7239304 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1067 |
| auto[1] |
4981537 |
1 |
|
|
T25 |
785 |
|
T28 |
396 |
|
T32 |
758 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11596976 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1804 |
| auto[1] |
623865 |
1 |
|
|
T25 |
48 |
|
T28 |
27 |
|
T32 |
122 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7226827 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
837 |
| auto[1] |
4994014 |
1 |
|
|
T25 |
1015 |
|
T28 |
459 |
|
T29 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2197589 |
1 |
|
|
T25 |
553 |
|
T28 |
256 |
|
T29 |
8 |
| auto[1] |
auto[0] |
auto[1] |
314046 |
1 |
|
|
T25 |
30 |
|
T28 |
16 |
|
T32 |
50 |
| auto[1] |
auto[1] |
auto[0] |
2172560 |
1 |
|
|
T25 |
414 |
|
T28 |
176 |
|
T32 |
296 |
| auto[1] |
auto[1] |
auto[1] |
309819 |
1 |
|
|
T25 |
18 |
|
T28 |
11 |
|
T32 |
72 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |