Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7211874 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
750 |
| auto[1] |
5008967 |
1 |
|
|
T25 |
1102 |
|
T28 |
497 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11596127 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1831 |
| auto[1] |
624714 |
1 |
|
|
T25 |
21 |
|
T28 |
20 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7232671 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1024 |
| auto[1] |
4988170 |
1 |
|
|
T25 |
828 |
|
T28 |
522 |
|
T29 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2174937 |
1 |
|
|
T25 |
305 |
|
T28 |
210 |
|
T29 |
6 |
| auto[1] |
auto[0] |
auto[1] |
310601 |
1 |
|
|
T25 |
10 |
|
T28 |
11 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2188519 |
1 |
|
|
T25 |
502 |
|
T28 |
292 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[1] |
314113 |
1 |
|
|
T25 |
11 |
|
T28 |
9 |
|
T32 |
93 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |