Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7233665 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
903 |
| auto[1] |
4987176 |
1 |
|
|
T25 |
949 |
|
T28 |
499 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11598658 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1816 |
| auto[1] |
622183 |
1 |
|
|
T25 |
36 |
|
T28 |
19 |
|
T32 |
140 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7242292 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
813 |
| auto[1] |
4978549 |
1 |
|
|
T25 |
1039 |
|
T28 |
490 |
|
T29 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2182787 |
1 |
|
|
T25 |
487 |
|
T28 |
185 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
311880 |
1 |
|
|
T25 |
21 |
|
T28 |
5 |
|
T32 |
84 |
| auto[1] |
auto[1] |
auto[0] |
2173579 |
1 |
|
|
T25 |
516 |
|
T28 |
286 |
|
T32 |
263 |
| auto[1] |
auto[1] |
auto[1] |
310303 |
1 |
|
|
T25 |
15 |
|
T28 |
14 |
|
T32 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |