Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7236722 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
989 |
| auto[1] |
4984119 |
1 |
|
|
T25 |
863 |
|
T28 |
442 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10137391 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1608 |
| auto[1] |
2083450 |
1 |
|
|
T25 |
244 |
|
T28 |
269 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7221116 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
785 |
| auto[1] |
4999725 |
1 |
|
|
T25 |
1067 |
|
T28 |
353 |
|
T29 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1465166 |
1 |
|
|
T25 |
427 |
|
T28 |
32 |
|
T29 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1045764 |
1 |
|
|
T25 |
114 |
|
T28 |
94 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1451109 |
1 |
|
|
T25 |
396 |
|
T28 |
52 |
|
T32 |
212 |
| auto[1] |
auto[1] |
auto[1] |
1037686 |
1 |
|
|
T25 |
130 |
|
T28 |
175 |
|
T32 |
217 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |