Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7246773 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
968 |
| auto[1] |
4974068 |
1 |
|
|
T25 |
884 |
|
T28 |
321 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10138686 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1635 |
| auto[1] |
2082155 |
1 |
|
|
T25 |
217 |
|
T28 |
348 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7229664 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
868 |
| auto[1] |
4991177 |
1 |
|
|
T25 |
984 |
|
T28 |
463 |
|
T29 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1462601 |
1 |
|
|
T25 |
461 |
|
T28 |
66 |
|
T32 |
257 |
| auto[1] |
auto[0] |
auto[1] |
1045283 |
1 |
|
|
T25 |
90 |
|
T28 |
221 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1446421 |
1 |
|
|
T25 |
306 |
|
T28 |
49 |
|
T32 |
160 |
| auto[1] |
auto[1] |
auto[1] |
1036872 |
1 |
|
|
T25 |
127 |
|
T28 |
127 |
|
T32 |
157 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |