Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7204176 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
928 |
| auto[1] |
5016665 |
1 |
|
|
T25 |
924 |
|
T28 |
508 |
|
T32 |
744 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10133938 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1734 |
| auto[1] |
2086903 |
1 |
|
|
T25 |
118 |
|
T28 |
242 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7216888 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1041 |
| auto[1] |
5003953 |
1 |
|
|
T25 |
811 |
|
T28 |
384 |
|
T29 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1451224 |
1 |
|
|
T25 |
344 |
|
T28 |
80 |
|
T29 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1043545 |
1 |
|
|
T25 |
47 |
|
T28 |
52 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1465826 |
1 |
|
|
T25 |
349 |
|
T28 |
62 |
|
T32 |
188 |
| auto[1] |
auto[1] |
auto[1] |
1043358 |
1 |
|
|
T25 |
71 |
|
T28 |
190 |
|
T32 |
244 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |