Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7240899 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
906 |
| auto[1] |
4979942 |
1 |
|
|
T25 |
946 |
|
T28 |
287 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10150281 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1671 |
| auto[1] |
2070560 |
1 |
|
|
T25 |
181 |
|
T28 |
308 |
|
T29 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7265698 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
906 |
| auto[1] |
4955143 |
1 |
|
|
T25 |
946 |
|
T28 |
418 |
|
T29 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1450368 |
1 |
|
|
T25 |
419 |
|
T28 |
76 |
|
T32 |
162 |
| auto[1] |
auto[0] |
auto[1] |
1044560 |
1 |
|
|
T25 |
97 |
|
T28 |
200 |
|
T29 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1434215 |
1 |
|
|
T25 |
346 |
|
T28 |
34 |
|
T32 |
160 |
| auto[1] |
auto[1] |
auto[1] |
1026000 |
1 |
|
|
T25 |
84 |
|
T28 |
108 |
|
T32 |
142 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |