Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7211082 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
999 |
| auto[1] |
5009759 |
1 |
|
|
T25 |
853 |
|
T28 |
502 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11600700 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1819 |
| auto[1] |
620141 |
1 |
|
|
T25 |
33 |
|
T28 |
20 |
|
T32 |
183 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7254721 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
962 |
| auto[1] |
4966120 |
1 |
|
|
T25 |
890 |
|
T28 |
448 |
|
T29 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2182447 |
1 |
|
|
T25 |
452 |
|
T28 |
174 |
|
T29 |
16 |
| auto[1] |
auto[0] |
auto[1] |
312051 |
1 |
|
|
T25 |
21 |
|
T28 |
8 |
|
T32 |
89 |
| auto[1] |
auto[1] |
auto[0] |
2163532 |
1 |
|
|
T25 |
405 |
|
T28 |
254 |
|
T32 |
415 |
| auto[1] |
auto[1] |
auto[1] |
308090 |
1 |
|
|
T25 |
12 |
|
T28 |
12 |
|
T32 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |