Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7214373 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
912 |
| auto[1] |
5006468 |
1 |
|
|
T25 |
940 |
|
T28 |
395 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10129303 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1607 |
| auto[1] |
2091538 |
1 |
|
|
T25 |
245 |
|
T28 |
272 |
|
T32 |
483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7206278 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
938 |
| auto[1] |
5014563 |
1 |
|
|
T25 |
914 |
|
T28 |
371 |
|
T29 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1454718 |
1 |
|
|
T25 |
343 |
|
T28 |
41 |
|
T29 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1045692 |
1 |
|
|
T25 |
140 |
|
T28 |
155 |
|
T32 |
237 |
| auto[1] |
auto[1] |
auto[0] |
1468307 |
1 |
|
|
T25 |
326 |
|
T28 |
58 |
|
T32 |
229 |
| auto[1] |
auto[1] |
auto[1] |
1045846 |
1 |
|
|
T25 |
105 |
|
T28 |
117 |
|
T32 |
246 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |