Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7201343 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
980 |
| auto[1] |
5019498 |
1 |
|
|
T25 |
872 |
|
T28 |
420 |
|
T32 |
715 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10134923 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1661 |
| auto[1] |
2085918 |
1 |
|
|
T25 |
191 |
|
T28 |
289 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7218847 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
990 |
| auto[1] |
5001994 |
1 |
|
|
T25 |
862 |
|
T28 |
365 |
|
T29 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1451531 |
1 |
|
|
T25 |
364 |
|
T28 |
32 |
|
T32 |
267 |
| auto[1] |
auto[0] |
auto[1] |
1035879 |
1 |
|
|
T25 |
77 |
|
T28 |
126 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1464545 |
1 |
|
|
T25 |
307 |
|
T28 |
44 |
|
T32 |
189 |
| auto[1] |
auto[1] |
auto[1] |
1050039 |
1 |
|
|
T25 |
114 |
|
T28 |
163 |
|
T32 |
230 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |