Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7210710 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
830 |
| auto[1] |
5010131 |
1 |
|
|
T25 |
1022 |
|
T28 |
558 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10132970 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1681 |
| auto[1] |
2087871 |
1 |
|
|
T25 |
171 |
|
T28 |
406 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7214153 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
998 |
| auto[1] |
5006688 |
1 |
|
|
T25 |
854 |
|
T28 |
507 |
|
T29 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1455756 |
1 |
|
|
T25 |
269 |
|
T28 |
30 |
|
T32 |
233 |
| auto[1] |
auto[0] |
auto[1] |
1041739 |
1 |
|
|
T25 |
78 |
|
T28 |
132 |
|
T32 |
246 |
| auto[1] |
auto[1] |
auto[0] |
1463061 |
1 |
|
|
T25 |
414 |
|
T28 |
71 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1046132 |
1 |
|
|
T25 |
93 |
|
T28 |
274 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |