Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7253458 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1043 |
| auto[1] |
4967383 |
1 |
|
|
T25 |
809 |
|
T28 |
457 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10136760 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1605 |
| auto[1] |
2084081 |
1 |
|
|
T25 |
247 |
|
T28 |
373 |
|
T32 |
271 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7220094 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
791 |
| auto[1] |
5000747 |
1 |
|
|
T25 |
1061 |
|
T28 |
479 |
|
T29 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1468323 |
1 |
|
|
T25 |
445 |
|
T28 |
51 |
|
T29 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1046678 |
1 |
|
|
T25 |
166 |
|
T28 |
185 |
|
T32 |
158 |
| auto[1] |
auto[1] |
auto[0] |
1448343 |
1 |
|
|
T25 |
369 |
|
T28 |
55 |
|
T32 |
87 |
| auto[1] |
auto[1] |
auto[1] |
1037403 |
1 |
|
|
T25 |
81 |
|
T28 |
188 |
|
T32 |
113 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |