Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7245957 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
978 |
| auto[1] |
4974884 |
1 |
|
|
T25 |
874 |
|
T28 |
300 |
|
T32 |
827 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10137851 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1573 |
| auto[1] |
2082990 |
1 |
|
|
T25 |
279 |
|
T28 |
282 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7236385 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
766 |
| auto[1] |
4984456 |
1 |
|
|
T25 |
1086 |
|
T28 |
350 |
|
T29 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1459090 |
1 |
|
|
T25 |
497 |
|
T28 |
45 |
|
T32 |
179 |
| auto[1] |
auto[0] |
auto[1] |
1046046 |
1 |
|
|
T25 |
155 |
|
T28 |
200 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1442376 |
1 |
|
|
T25 |
310 |
|
T28 |
23 |
|
T32 |
268 |
| auto[1] |
auto[1] |
auto[1] |
1036944 |
1 |
|
|
T25 |
124 |
|
T28 |
82 |
|
T32 |
244 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |