Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7292789 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1098 |
| auto[1] |
4928052 |
1 |
|
|
T25 |
754 |
|
T28 |
452 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10135674 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1713 |
| auto[1] |
2085167 |
1 |
|
|
T25 |
139 |
|
T28 |
220 |
|
T32 |
479 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7226031 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1002 |
| auto[1] |
4994810 |
1 |
|
|
T25 |
850 |
|
T28 |
304 |
|
T29 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1474999 |
1 |
|
|
T25 |
399 |
|
T28 |
38 |
|
T29 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1053714 |
1 |
|
|
T25 |
111 |
|
T28 |
99 |
|
T32 |
252 |
| auto[1] |
auto[1] |
auto[0] |
1434644 |
1 |
|
|
T25 |
312 |
|
T28 |
46 |
|
T32 |
270 |
| auto[1] |
auto[1] |
auto[1] |
1031453 |
1 |
|
|
T25 |
28 |
|
T28 |
121 |
|
T32 |
227 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |