Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7215054 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
892 |
| auto[1] |
5005787 |
1 |
|
|
T25 |
960 |
|
T28 |
398 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10134625 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1713 |
| auto[1] |
2086216 |
1 |
|
|
T25 |
139 |
|
T28 |
327 |
|
T32 |
373 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219624 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1073 |
| auto[1] |
5001217 |
1 |
|
|
T25 |
779 |
|
T28 |
381 |
|
T32 |
846 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1448463 |
1 |
|
|
T25 |
253 |
|
T28 |
30 |
|
T32 |
252 |
| auto[1] |
auto[0] |
auto[1] |
1044845 |
1 |
|
|
T25 |
86 |
|
T28 |
171 |
|
T32 |
184 |
| auto[1] |
auto[1] |
auto[0] |
1466538 |
1 |
|
|
T25 |
387 |
|
T28 |
24 |
|
T32 |
221 |
| auto[1] |
auto[1] |
auto[1] |
1041371 |
1 |
|
|
T25 |
53 |
|
T28 |
156 |
|
T32 |
189 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |