Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7207480 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1016 |
| auto[1] |
5013361 |
1 |
|
|
T25 |
836 |
|
T28 |
404 |
|
T32 |
797 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11594393 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1818 |
| auto[1] |
626448 |
1 |
|
|
T25 |
34 |
|
T28 |
15 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7222185 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
878 |
| auto[1] |
4998656 |
1 |
|
|
T25 |
974 |
|
T28 |
362 |
|
T29 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2197348 |
1 |
|
|
T25 |
518 |
|
T28 |
148 |
|
T29 |
17 |
| auto[1] |
auto[0] |
auto[1] |
314831 |
1 |
|
|
T25 |
19 |
|
T28 |
4 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2174860 |
1 |
|
|
T25 |
422 |
|
T28 |
199 |
|
T32 |
496 |
| auto[1] |
auto[1] |
auto[1] |
311617 |
1 |
|
|
T25 |
15 |
|
T28 |
11 |
|
T32 |
119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |