Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7217581 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1002 |
| auto[1] |
5003260 |
1 |
|
|
T25 |
850 |
|
T28 |
513 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10135513 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1643 |
| auto[1] |
2085328 |
1 |
|
|
T25 |
209 |
|
T28 |
382 |
|
T32 |
602 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7233667 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
980 |
| auto[1] |
4987174 |
1 |
|
|
T25 |
872 |
|
T28 |
470 |
|
T29 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1442476 |
1 |
|
|
T25 |
380 |
|
T28 |
23 |
|
T29 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1037036 |
1 |
|
|
T25 |
113 |
|
T28 |
152 |
|
T32 |
272 |
| auto[1] |
auto[1] |
auto[0] |
1459370 |
1 |
|
|
T25 |
283 |
|
T28 |
65 |
|
T32 |
305 |
| auto[1] |
auto[1] |
auto[1] |
1048292 |
1 |
|
|
T25 |
96 |
|
T28 |
230 |
|
T32 |
330 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |