Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7230170 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1039 |
| auto[1] |
4990671 |
1 |
|
|
T25 |
813 |
|
T28 |
465 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10142996 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1651 |
| auto[1] |
2077845 |
1 |
|
|
T25 |
201 |
|
T28 |
329 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7234188 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1122 |
| auto[1] |
4986653 |
1 |
|
|
T25 |
730 |
|
T28 |
400 |
|
T29 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1461336 |
1 |
|
|
T25 |
278 |
|
T28 |
30 |
|
T32 |
277 |
| auto[1] |
auto[0] |
auto[1] |
1041707 |
1 |
|
|
T25 |
103 |
|
T28 |
172 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1447472 |
1 |
|
|
T25 |
251 |
|
T28 |
41 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1036138 |
1 |
|
|
T25 |
98 |
|
T28 |
157 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |