Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219950 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1079 |
| auto[1] |
5000891 |
1 |
|
|
T25 |
773 |
|
T28 |
468 |
|
T29 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10135242 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1580 |
| auto[1] |
2085599 |
1 |
|
|
T25 |
272 |
|
T28 |
313 |
|
T32 |
426 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7226342 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
909 |
| auto[1] |
4994499 |
1 |
|
|
T25 |
943 |
|
T28 |
401 |
|
T32 |
857 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1453133 |
1 |
|
|
T25 |
401 |
|
T28 |
36 |
|
T32 |
224 |
| auto[1] |
auto[0] |
auto[1] |
1042941 |
1 |
|
|
T25 |
143 |
|
T28 |
130 |
|
T32 |
225 |
| auto[1] |
auto[1] |
auto[0] |
1455767 |
1 |
|
|
T25 |
270 |
|
T28 |
52 |
|
T32 |
207 |
| auto[1] |
auto[1] |
auto[1] |
1042658 |
1 |
|
|
T25 |
129 |
|
T28 |
183 |
|
T32 |
201 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |