Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7218680 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
991 |
| auto[1] |
5002161 |
1 |
|
|
T25 |
861 |
|
T28 |
304 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11598793 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1811 |
| auto[1] |
622048 |
1 |
|
|
T25 |
41 |
|
T28 |
14 |
|
T32 |
213 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7247164 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
816 |
| auto[1] |
4973677 |
1 |
|
|
T25 |
1036 |
|
T28 |
477 |
|
T29 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2180860 |
1 |
|
|
T25 |
472 |
|
T28 |
293 |
|
T29 |
8 |
| auto[1] |
auto[0] |
auto[1] |
311315 |
1 |
|
|
T25 |
16 |
|
T28 |
8 |
|
T32 |
116 |
| auto[1] |
auto[1] |
auto[0] |
2170769 |
1 |
|
|
T25 |
523 |
|
T28 |
170 |
|
T32 |
440 |
| auto[1] |
auto[1] |
auto[1] |
310733 |
1 |
|
|
T25 |
25 |
|
T28 |
6 |
|
T32 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |