Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7201849 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1015 |
| auto[1] |
5018992 |
1 |
|
|
T25 |
837 |
|
T28 |
460 |
|
T32 |
818 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11596563 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1812 |
| auto[1] |
624278 |
1 |
|
|
T25 |
40 |
|
T28 |
17 |
|
T32 |
160 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7239809 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
921 |
| auto[1] |
4981032 |
1 |
|
|
T25 |
931 |
|
T28 |
370 |
|
T29 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2168080 |
1 |
|
|
T25 |
472 |
|
T28 |
210 |
|
T29 |
13 |
| auto[1] |
auto[0] |
auto[1] |
310454 |
1 |
|
|
T25 |
13 |
|
T28 |
11 |
|
T32 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2188674 |
1 |
|
|
T25 |
419 |
|
T28 |
143 |
|
T32 |
319 |
| auto[1] |
auto[1] |
auto[1] |
313824 |
1 |
|
|
T25 |
27 |
|
T28 |
6 |
|
T32 |
67 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |