Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7220627 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
987 |
| auto[1] |
5000214 |
1 |
|
|
T25 |
865 |
|
T28 |
464 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11592202 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1816 |
| auto[1] |
628639 |
1 |
|
|
T25 |
36 |
|
T28 |
16 |
|
T32 |
191 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7202830 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
967 |
| auto[1] |
5018011 |
1 |
|
|
T25 |
885 |
|
T28 |
391 |
|
T29 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2180176 |
1 |
|
|
T25 |
436 |
|
T28 |
178 |
|
T29 |
2 |
| auto[1] |
auto[0] |
auto[1] |
311940 |
1 |
|
|
T25 |
20 |
|
T28 |
7 |
|
T32 |
74 |
| auto[1] |
auto[1] |
auto[0] |
2209196 |
1 |
|
|
T25 |
413 |
|
T28 |
197 |
|
T29 |
11 |
| auto[1] |
auto[1] |
auto[1] |
316699 |
1 |
|
|
T25 |
16 |
|
T28 |
9 |
|
T32 |
117 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |