Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7228436 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
852 |
| auto[1] |
4992405 |
1 |
|
|
T25 |
1000 |
|
T28 |
291 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11599296 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1826 |
| auto[1] |
621545 |
1 |
|
|
T25 |
26 |
|
T28 |
20 |
|
T32 |
122 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7249324 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1032 |
| auto[1] |
4971517 |
1 |
|
|
T25 |
820 |
|
T28 |
513 |
|
T32 |
679 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2184735 |
1 |
|
|
T25 |
360 |
|
T28 |
283 |
|
T32 |
266 |
| auto[1] |
auto[0] |
auto[1] |
312598 |
1 |
|
|
T25 |
13 |
|
T28 |
13 |
|
T32 |
59 |
| auto[1] |
auto[1] |
auto[0] |
2165237 |
1 |
|
|
T25 |
434 |
|
T28 |
210 |
|
T32 |
291 |
| auto[1] |
auto[1] |
auto[1] |
308947 |
1 |
|
|
T25 |
13 |
|
T28 |
7 |
|
T32 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |